NDLI: Evaluating optimizations for multiprocessors e-commerce server running TPC-W workload

Content Provider	IEEE Xplore Digital Library
Author	Foglia, P. Giorgi, R. Prete, C.A.
Copyright Year	2001
Description	Author affiliation: Dipartimento di Inf., Pisa Univ., Italy (Foglia, P.; Giorgi, R.; Prete, C.A.)
Abstract	The performance of an electronic commerce server, i.e. a system running electronic commerce applications is evaluated in the case of shared-bus multiprocessor architecture. In particular, we focused on the memory subsystem design and the analysis of coherence related overhead when the running software is set up as specified in the TPC-W benchmark. Our aim is to individuate main factors that limit performance in such a system, and the main optimization that can be done to speed up the execution of e-commerce workload on SMP architecture. Our results show that: (i) we need an accurate redesign of kernel data structure for large cache size; (ii) cache affinity is useful in reducing cold and replacement miss, but it is not effective in every load condition; (iii) passive sharing, i.e. the sharing induced by process migration, is a cause of performance degradation. A Write-Update protocol that correctly treats passive sharing (namely PSCR) permits two beneficial effects: increases performance in every situation and increases system scalability (up to 20 processor are permitted in our configuration).
Sponsorship	Univ. Hawaii College of Bus. Adm
File Size	596090
File Format	PDF
ISBN	0769509819
DOI	10.1109/HICSS.2001.927077
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2001-01-06
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Protocols Computer architecture Electronic commerce Scalability Network servers Cache memory File servers Application software Kernel Data structures
Content Type	Text
Resource Type	Article

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