NDLI: Double Gate Tunnel FET with ultrathin silicon body and high-k gate dielectric

Please wait, while we are loading the content...

2015 45th European Solid State Device Research Conference (ESSDERC)

2014 44th European Solid State Device Research Conference (ESSDERC)

2013 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

2012 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

2011 Proceedings of the European Solid-State Device Research Conference (ESSDERC)

2010 Proceedings of the European Solid State Device Research Conference

2009 Proceedings of the European Solid State Device Research Conference

ESSDERC 2008 - 38th European Solid-State Device Research Conference

ESSDERC 2007 - 37th European Solid State Device Research Conference

2006 European Solid-State Device Research Conference

Proceedings contents

Conference Committee

Technical Co-Sponsors

Table of contents

Mobile Friendly Rollable Displays

Perspective of Low-Power and High-Speed Wireless Inter-Chip Communications for SiP Integration

Integrated Micromechanical Circuits for RF Front Ends

Single-Electron Transistors and Circuits for Future Ubiquitous Computing Applications

Design methodologies and tools for circuit design in CMOS nanometer technologies

Nanotransistors: A Bottom-Up View

An industrial view on compact modeling

FinFET: the prospective multi-gate device for future SoC applications

Analog and RF circuits in 45 nm CMOS and below: planar bulk versus FinFET

Analysis of power dissipation in clocked Quantum Cellular Automaton circuits

AlN Contour-Mode Vibrating RF MEMS for Next Generation Wireless Communications

Multi-Gate MOSFET Design

Circuit Techniques for Organic and Amorphous Semiconductor based Field Effect Transistors

Independent-Gate Controlled Asymmetrical SRAM Cells in Double-Gate MOSFET Technology for Improved READ Stability

A High Performance pMOSFET with Two-step Recessed SiGe-S/D Structure for 32nm node and Beyond

A planar transistor for the 32-nm node and beyond with an ultra-shallow junction fabricated using in-situ doped selective Si epitaxy

Ultra-Thin-Body P-MOSFET Featuring Silicon-Germanium Source/Drain Stressors With High Germanium Content Formed by Local Condensation

Carrier Backscattering Characteristics of Strained N-MOSFET Featuring Silicon-Carbon Source/Drain Regions

Electron mobility enhancement in uniaxially strained MOSFETs: Extraction of the effective mass variation

Quantifying Self-Heating Effects in Strained Si MOSFETs with Scaling

STI Effect on Flicker Noise in 0.13-μm RF NMOS

Generation Recombination Noise in Dual Channel AlGaN/GaN High Electron Mobility Transistor

Work Function Investigation in Advanced Metal Gate-HfO2-SiO2 Systems with Bevel Structures

Systematic Gate Stack Optimization to Maximize Mobility with HfSiON EOT Scaling

Dual phase TOSI-gate process on High-K dielectrics in a CMP-less flow

High Performance pMOSFET with ALD-TiN/HfO2 Gate Stack on (110) Substrate by Low Temperature Process

On-Chip RF Detection of DNA Hybridization Based on Interdigitated Al/Al2O3 Capacitors

A miniaturized multiwire proportional chamber using CMOS wafer scale post-processing

Modeling of a CMOS Convective Accelerometer for HDL integration

Design And Analysis Of A Capacitive Vibration-To-Electrical Energy Converter With Built-In Voltage

Germanium FETs and capacitors with rare earth CeO2/HfO2 gates

New TIT Capacitor with ZrO2/Al2O3/ZrO2 dielectrics for 60nm and below DRAMs

Approaches to CMOS integration of epitaxial gadolinium oxide high-K dielectrics

CMOS Compatible Dual Metal Gate Integration with Successful Vth Adjustment on High-k HfTaON by High-Temperature Metal Intermixing

First ultra-thin film FDSOI devices with CMP-less TOtally SIlicided (TOSI) gate Integration

Monte-Carlo Simulation of Decananometric Double-Gate SOI devices: Multi-Subband vs. 3D-Electron Gas with Quantum Corrections

Assessment of the Impact of Biaxial Strain on the Drain Current of Decanometric n-MOSFET

Effects of the Band-Structure Modification in Silicon Nanowires with Small Diameters

Monte Carlo Simulation of the Performance Dependence on Surface and Channel Orientation in Scaled pFinFETs

Orientation Dependence of the Low Field Mobility in Double-and Single-gate SOI FETs

One and Two Port Piezoelectric Contour-Mode MEMS Resonators for Frequency Synthesis

Above IC integrated SrTiO3 high K MIM capacitors

High Quality Factor Copper Inductors on Wafer-Level Quartz Package for RF MEMS Applications

On-Chip Integrated Inductors with Ni-Zn-Cu-Fe and Y-Bi-Fe Ferrite Thin-films for RF IC

Design and Manufacturing of Small Area On-Chip-Antenna (OCA) for RFID Tags

Threshold voltage dispersion and impurity scattering limited mobility in carbon nanotube field effect transistors with randomly doped reservoirs

Carbon nanotube field-effect transistor for GHz operation

Optimal Design for Carbon Nanotube Transistors

Ge-catalyzed Vapour-Liquid-Solid growth of Carbon Nanotubes

New Floating Gate Self-Aligning Technology for Multilevel NOR Flash Memory

A Novel Channel-Program-Erase Technique with Substrate Transient Hot Carrier Injection for SONOS Memory Application

VDNROM: A Novel Four-Bits-Per-Cell Vertical Channel Dual-Nitride-Trapping-Layer ROM for High Density Flash Memory Applications

Analysis of a Novel Electrically Programmable Active Fuse for Advanced CMOS SOI One-Time Programmable Memory Applications

Reliability Comparison of Al2O3 and HfSiON for use as Interpoly Dielectric in Flash Arrays

Al2O3 Based Flash Interpoly Dielectrics: a Comparative Retention Study

In-depth Investigation of HfAlO Layers as Interpoly Dielectrics of Future Flash Memories

Evaluation of the degradation of floating-gate memories with Al2O3 tunnel oxide

Retention Tail Improvement for Gbit DRAMs through Trap Passivation confirmed by Activation Energy Analysis

Drain leakage fluctuation reduction in the recessed channel array transistor DRAM with the elevated source-drain

Impact of Random Dopant Fluctuation on Bulk CMOS 6-T SRAM Scaling

Scaling aspects of microjoints for 3D chip interconnects

Investigations on an Isolated Lateral High-Voltage n-channel LDMOS Transistor with a Typical Breakdown of 150V

A Highly Scalable High Voltage MOSFET Model

Power trench MOSFETs with very low specific on-resistance for 25V applications

Integrated VDMOS transistor with reduced JFET effect

Effects of an Fe-doped GaN Buffer in AlGaN/GaN Power HEMTs on Si Substrate

Experimental and simulation study of the Schottky barrier lowering by substrate doping variation for PtSi Source/Drain SBFETs

Dopant-Segregated Ni-Silicide Schottky-Source/Drain CMOS on Strained-Si/SiGe Multiple Quantum-Well Channel on Bulk-Si

Schottky Tunneling Source MOSFET Design for Mixed Mode and Analog Applications

Fabrication and Analysis of CMOS Fully-Compatible High Conductance Impact-Ionization MOS (I-MOS) Transistors

Co-integration of 2 mV/dec Subthreshold Slope Impact Ionization MOS (I-MOS) with CMOS

Partitioning Scheme in Lateral Asymmetric MOST

Self Heating Simulation of Multi-Gate FETs

Statistical Exploration of the Dual Supply Voltage Space of a 65nm PD/SOI CMOS SRAM Cell

Geometry Optimization of Sub-100nm Node RF CMOS Utilizing Three Dimensional TCAD Simulation

Extrinsic, Parasitic Capacitance Contributions of MOSFETs, their Impact on Performance, and their Modeling

Novel Retinal Prosthesis System with Three Dimensionally Stacked LSI Chip

Fixed-Pattern Noise Induced by Transmission Gate in Pinned 4T CMOS Image Sensor Pixels

InGaAs/InP Single Photon Avalanche Diode Design and Characterization

Improved organic light-emitting devices with tunable IV by inserting a hole-blocking layer between hole-injecting layer and hole-transporting layer

Highly Reliable TiN/ZrO2/TiN 3D Stacked Capacitors for 45 nm Embedded DRAM Technologies

High Performance 65nm SOI Transistors Using Laser Spike Annealing

LASER Anneal to Enable Ultimate CMOS Scaling with PMOS Band Edge Metal Gate/High-K Stacks

Superior N- and PMOSFET scalability using carbon co-implantation and spike annealing

Local volume inversion and corner effects in triangular gate-all-around MOSFETs

Effective Mobility Extraction Based on a Split RF C-V Method for Short-Channel FinFETs

Experimental Evidence of Mobility Enhancement in Short-Channel Ultra-thin Body Double-Gate MOSFETs

Design Considerations and Comparative Investigation of Ultra-Thin SOI, Double-Gate and Cylindrical Nanowire FETs

Experimental Evidence for Reduction of Gate Tunneling Current in FinFET Structures and Its Dependence on the Fin Width

High Threshold Voltage Matching Performance on Gate-All-Around MOSFET

Double Gate Tunnel FET with ultrathin silicon body and high-k gate dielectric

A Novel Bias Temperature Instability Characterization Methodology for High-k MOSFETs

Investigation of the high temperature stability of TiN-Al2O3-TiN capacitors for sub 50nm deep trench DRAM

Cross-wafer controlled interface layer thickness variation, and its application to $SiO_{2}$ / high-κ stack characterisation

The Analysis of Dielectric Breakdown in Cu/Low-k Interconnect System

Does Multi-Trap Assisted Tunneling explain the oxide thickness dependence of the Statistics of SILC in FLASH Memory Arrays?

A Study of the As-Processed and Generated Leakage Paths in Al2O3-Based Dielectric Stacks for Nonvolatile Memory Applications

Detection of Single-Electron Transfer Events and Capacitance Measurements in Submicron Floating-Gate Memory Cells

Reliability of Recess-channel Gate Cell Transistor under Gate-Induced Drain Leakage Stress and Positive Bias Fowler-Nordheim Gate Stress

Fast Kerf- and Tester-Compatible Method for RC Characterization of DRAM Memory Cells

Non-Linear Gate Length Dependence of On-Current in Si-Nanowire FETs

Low temperature single electron characteristics in gate-all-around MOSFETs

Thermoelectric and Thermionic Micro-Converters

Semi-insulating Czochralski-silicon for Radio Frequency Applications

Fluoride Resonant Tunneling Diodes using Lattice-Matched Buffer Layers on Si Substrates

Validity Of The Flat Band Perturbation Technique In Non-Ohmic Region

Model for electron redistribution in silicon nitride

Impact of Fermi level pinning at polysilicon gate grain boundaries on nano-MOSFET variability: A 3-D simulation study

Analytical modelling of large signal cyclo-stationary low frequency noise for arbitrary periodic input

Temperature Dependent Dielectric Absorption of MIM Capacitors: RF Characterization and Modeling

Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005.

Proceedings of the 30th European Solid-State Circuits Conference (IEEE Cat. No.04EX850)

ESSDERC '03. 33rd Conference on European Solid-State Device Research, 2003.

32nd European Solid-State Device Research Conference

31st European Solid-State Device Research Conference

30th European Solid-State Device Research Conference

29th European Solid-State Device Research Conference

28th European Solid-State Device Research Conference

27th European Solid-State Device Research Conference

ESSDERC '96: Proceedings of the 26th European Solid State Device Research Conference

ESSDERC '95: Proceedings of the 25th European Solid State Device Research Conference

ESSDERC '94: 24th European Solid State Device Research Conference

ESSDERC '93: 23rd European solid State Device Research Conference

ESSDERC '92: 22nd European Solid State Device Research conference

ESSDERC '91: 21st European Solid State Device Research Conference

ESSDERC '90: 20th European Solid State Device Research Conference

ESSDERC '89: 19th European Solid State Device Research Conference

ESSDERC '88: 18th European Solid State Device Research Conference

ESSDERC '87: 17th European Solid State Device Research Conference

Double Gate Tunnel FET with ultrathin silicon body and high-k gate dielectric

Content Provider	IEEE Xplore Digital Library
Author	Boucart, K. Ionescu, A.M.
Copyright Year	2006
Description	Author affiliation: Inst. of Microelectron. & Microsyst., Swiss Fed. Inst. of Technol. Lausanne (Boucart, K.; Ionescu, A.M.)
Abstract	In this paper we propose a novel design for a double gate tunnel field effect transistor (DG TFET), for which the simulations show significant improvements compared with single gate devices with a SiO $_{2}$ gate dielectric. For the first time, double gate devices using a high-K gate dielectric are explored, showing on-current as high as 1 mA for a gate voltage of 1.2 V, reduced off-current as low as 0.1 fA, improved average subthreshold swing of 52 mV/decade, and a minimum point slope of 18 mV/decade. An Ion/Ioff ratio of more than 1012 is shown
Starting Page	383
Ending Page	386
File Size	511353
Page Count	4
File Format	PDF
ISBN	1424403014
ISSN	19308876
DOI	10.1109/ESSDER.2006.307718
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-19
Publisher Place	Switzerland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Double-gate FETs Silicon Voltage Tunneling MOSFETs CMOS technology Dielectric devices Dielectric substrates Costs Fabrication
Content Type	Text
Resource Type	Article

Central Library (ISO-9001:2015 Certified)
Indian Institute of Technology Kharagpur
Kharagpur, West Bengal, India | PIN - 721302

See location in the Map
03222 282435
Mail: support@ndl.gov.in

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in