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Content Provider | IEEE Xplore Digital Library |
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Author | Rao, S.K. Hatamian, M. Uyttendaele, M.T. Narayan, S. O'Neill, J.H. Uvieghara, G.A. |
Copyright Year | 1993 |
Description | Author affiliation: Silicon Design Experts Inc., Lakewood, NJ, USA (Rao, S.K.; Hatamian, M.) |
Abstract | A 10.5-GOPS video encoder chip is described which implements CCITT H.261, P*64, and MPEG (Motion Picture Experts Group) (P-frame) encoding algorithms (including exhaustive motion estimation) at rates up to 30 frames/s with a resolution of up to 352*288 pixels per frame (CIF format). The chip accepts input video through either a video bus or a 16-b host bus and produces the final encoded bit stream in its output FIFO. A completely self-contained and glueless interface in this chip makes it possible to directly connect it to industry standard DRAM chips (1 MB) needed for frame store. The block diagram of the encoder chip is shown, and the characteristics of the major modules are listed. |
Starting Page | 32 |
Ending Page | 33 |
File Size | 516325 |
Page Count | 2 |
File Format | |
ISBN | 0780309871 |
DOI | 10.1109/ISSCC.1993.280096 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 1993-02-24 |
Publisher Place | USA |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Quantization Encoding Motion estimation Hardware Chromium System testing Communication system control Quadratic programming Engines Discrete cosine transforms |
Content Type | Text |
Resource Type | Article |
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