NDLI: A 300 MHz 115 W 32 b bipolar ECL microprocessor with on-chip caches

Content Provider	IEEE Xplore Digital Library
Author	Jouppi, N.P. Boyle, P. Dion, J. Doherty, M.J. Eustace, A. Haddad, R. Mayo, R. Menon, S. Monier, L. Stark, D. Turrini, S. Yang, L.
Copyright Year	1993
Description	Author affiliation: Digital Equipment Corp., Palo Alto, CA, USA (Jouppi, N.P.; Boyle, P.; Dion, J.; Doherty, M.J.; Eustace, A.; Haddad, R.; Mayo, R.; Menon, S.; Monier, L.; Stark, D.; Turrini, S.; Yang, L.)
Abstract	A full-custom 32-b ECL (emitter coupled logic) microprocessor which uses a 1.0- mu m-drawn single-poly technology with four layers of aluminum and one layer of gold interconnect is described. The 15.4-mm*12.6-mm die contains 468-k bipolar transistors (f/sub t/=13 GHz) and 206-k resistors. The chip implements a subset of an existing RISC (reduced instruction set computer) architecture. The machine has five pipeline stages, each one clock cycle long. A 128-b bus is used for incoming data; a 64-b bus is used for outgoing data. The chip uses a single-phase differential clock. The clock distribution network consists of three levels of H-trees. The 2-kB instruction and data caches use a 16-B line, contain byte parity, and are direct-mapped. The chip contains 30 internal master bias circuits, whose outputs are wire-ORed together. The logic portions of the chip primarily use a single-ended 575-mV swing.
Starting Page	84
Ending Page	85
File Size	595511
Page Count	2
File Format	PDF
ISBN	0780309871
DOI	10.1109/ISSCC.1993.280074
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-02-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Microprocessors Clocks Logic Aluminum Gold Integrated circuit interconnections Bipolar transistors Resistors Reduced instruction set computing Computer aided instruction
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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