NDLI: A 1.71 M-transistor CMOS CPU chip with a testable cache architecture

Content Provider	IEEE Xplore Digital Library
Author	Saito, Y. Shimazu, Y. Kobayashi, S. Shimizu, T. Matsuo, M. Ohtsuka, A. Shirai, K. Murata, H. Nishiwaki, Y. Fujioka, I. Nabeta, Y. Kanamoto, H. Hiraoka, S. Suzuki, T. Hinata, J. Shimotsuma, Y.
Copyright Year	1993
Description	Author affiliation: Mitsubishi Electric Corp., Hyogo, Japan (Saito, Y.; Shimazu, Y.; Kobayashi, S.; Shimizu, T.; Matsuo, M.; Ohtsuka, A.)
Abstract	A CISC CPU chip for the business computer is described. It contains an integer unit (IU), a double-precision floating-point unit (FPU), an address generation unit (AGU), and a Harvard-style memory unit with cache. The memory includes two independent memory management units (DMMU and IMMU), an 8-kB D-cache, a 32-B store buffer (SB), and a bus-controller unit (BCU). An on-chip PLL (phase-locked loop) synchronizes external and internal clock edges with a skew of 1-ns. The chip is fabricated in a 0.8- mu m CMOS double-polysilicon double-metal technology. A 77- mu m/sup 2/ SRAM (static random-access memory) cell uses a high resistance load formed by the second polysilicon layer. The 16.3-mm*12.7-mm chip contains 1.71-M transistors. In 40-MHz operation, power consumption is 6 W with a 5-V supply. The design is verified by simulations at several levels, using a microsimulator for evaluating parallelism of a large horizontal microprogram.
Starting Page	86
Ending Page	87
File Size	565140
Page Count	2
File Format	PDF
ISBN	0780309871
DOI	10.1109/ISSCC.1993.280073
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	1993-02-24
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Testing Memory management Phase locked loops CMOS technology Buffer storage Synchronization Clocks Random access memory Energy consumption Parallel processing
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

A 1.71-million transistor CMOS CPU chip with a testable cache architecture

A 0.5 /spl mu/m CMOS CNN analog random access memory chip for massive image processing

A single chip MPEG-1/CDROM decoder for video CD player applications

Coherence maintenances to realize an efficient parallel processing for a cache memory with synchronization on a chip-multiprocessor

A CMOS 100MHz Microprocessor

Super-compact shared-cache memories with low power consumption for multi-issue single chip processors

Injection-Locked Clocking: A New GHz Clock Distribution Scheme

A 40K cache memory and memory management unit

Low-Power Instruction Cache Architecture Using Pre-Tag Checking

A 1.71 M-transistor CMOS CPU chip with a testable cache architecture

Similar Documents

A 1.71-million transistor CMOS CPU chip with a testable cache architecture

A 0.5 /spl mu/m CMOS CNN analog random access memory chip for massive image processing

A single chip MPEG-1/CDROM decoder for video CD player applications

Coherence maintenances to realize an efficient parallel processing for a cache memory with synchronization on a chip-multiprocessor

A CMOS 100MHz Microprocessor

Super-compact shared-cache memories with low power consumption for multi-issue single chip processors

Injection-Locked Clocking: A New GHz Clock Distribution Scheme

A 40K cache memory and memory management unit

Low-Power Instruction Cache Architecture Using Pre-Tag Checking

A 1.71 M-transistor CMOS CPU chip with a testable cache architecture