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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Wang, Xingsheng Cheng, Binjie Millar, Campbell Reid, Dave Asenov, Asen |
| Copyright Year | 2014 |
| Description | Author affiliation: Gold Standard Simulations Ltd., Rankine Building, Oakfield Avenue, Glasgow G12 8LT, UK (Millar, Campbell; Reid, Dave) || Device Modelling Group, School of Engineering, University of Glasgow, G12 8LT, UK (Wang, Xingsheng; Cheng, Binjie; Asenov, Asen) |
| Abstract | Variability in nanoscale FinFETs brings huge challenges to SRAM design. Using recently developed unified variability compact models, in this paper we investigate the impact of long-range process variation and local statistical variability on various 6T-SRAM metrics including static noise margin, bitline write margin and retention leakage in two types of cell layout. The results show that these metrics are affected by different types of variability with different sensitivities. |
| Starting Page | 1 |
| Ending Page | 3 |
| File Size | 1566426 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781479932962 |
| e-ISBN | 9781479932825 |
| DOI | 10.1109/ICSICT.2014.7021284 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-10-28 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Integrated circuit modeling FinFETs Measurement Semiconductor process modeling Random access memory Layout |
| Content Type | Text |
| Resource Type | Article |
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