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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Wu, Yanwei Peng, Xiaohong Dong, Yang Liu, Miao |
| Copyright Year | 2014 |
| Description | Author affiliation: VLSI and System Lab, Beijing University of Technology, 100124, CHINA (Wu, Yanwei; Peng, Xiaohong; Dong, Yang; Liu, Miao) |
| Abstract | Because of high sampling rate and high resolution, pipeline ADC is widely used in system on chip (SOC). As sampling rate and resolution increasing, design difficulty is increasing. This paper analyzes restricts from amplifier in Pipeline ADC. By contrast with different amplifiers, this paper analyzes and designs a double nesting gain boosted amplifier in 14 bits 50 MS/s pipeline ADC. Under 1.2 V power supply, this amplifier achieves 103 dB DC gain, 1.34 GHz unity gain bandwidth, 88° phase margin. Transient simulation result shows a 45µV settling time error in 10 ns. The total consumption is 24 mW. |
| Starting Page | 1 |
| Ending Page | 3 |
| File Size | 1025537 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781479932962 |
| e-ISBN | 9781479932825 |
| DOI | 10.1109/ICSICT.2014.7021567 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2014-10-28 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Boosting Abstracts System-on-chip Education Transient analysis Simulation |
| Content Type | Text |
| Resource Type | Article |
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