NDLI: Heterogeneous integration of nano devices on Si CMOS platform

Content Provider	IEEE Xplore Digital Library
Author	Wang, K.L. Fei Liu Ostroumov, R.
Copyright Year	2004
Description	Author affiliation: Dept. of Electr. Eng., California Univ., Los Angeles, CA, USA (Wang, K.L.; Fei Liu; Ostroumov, R.)
Abstract	This paper outlines the limits on traditional scaling of CMOS and beyond, as well as the possibilities of introducing novel materials, their devices and the organization of these structures. From these organized structures, new local information processing architectures beyond CMOS may be possible. In addition to achieving continuous improvement of performance following Moore's Law, another benefit of integration is to have more functions on a Si platform. Thus, the potential of heterogeneous integration of self-assembly wires, dots,and molecules, with nanometer scale feature sizes on a Si CMOS platform may lead to future integrated nanosystems, incorporating many functions beyond traditional electronics. Nanostructures enable reduction of defects and they may be formed without rigid conformation to the crystalline structure of the substrates, or in other words, they are relatively free from constraint of the crystalline substrates. Thus, high performance devices and circuits may be integrated in a large area. One of the major issues for continuous increase of integration level is the increase of power dissipation per unit area on chip. We examine this critical issue of integrated circuits from a fundamental point of view of power dissipation. In order to alleviate the power dissipation issue, we study locally active devices, which may be built from homogeneous to form computational systems. Systems, such as cellular automata, cellular nonlinear networks, and other similar architectures, may be explored for low power application using nanometer scale devices and their integration.
Starting Page	228
Ending Page	233
File Size	1132071
Page Count	6
File Format	PDF
ISBN	078038511X
DOI	10.1109/ICSICT.2004.1434994
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-18
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Power dissipation Crystallization Information processing CMOS process Continuous improvement Moore's Law Self-assembly Wires Nanostructures Circuits
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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