NDLI: Scaling of shallow trench isolation with stress control for 65nm node and beyond

Content Provider	IEEE Xplore Digital Library
Author	Kuroi, T. Horita, K.
Copyright Year	2004
Description	Author affiliation: Renesas Technol. Corp., Itami, Japan (Kuroi, T.; Horita, K.)
Abstract	A progressive scaling of both intra- and inter-well isolation has been carried out for SoC (system on chip) with 65nm technology node and beyond, resulting in increased chip speed, increased transistor density, and lower cost performance. Shallow trench isolation (STI) with almost no encroachment, good planarity, higher isolation property, is a most promising isolation scheme for ULSI application (Faza et al., 1993; Bryant et al., 1994; Nandakumar et al., 1998). However, this rapid scaling of STI needs several difficult challenges from the viewpoints of both the process technology and the device property. In this paper, the major issues for STI scaling are described and some solutions are discussed to overcome the scaling crisis.
Starting Page	548
Ending Page	553
File Size	1495142
Page Count	6
File Format	PDF
ISBN	078038511X
DOI	10.1109/ICSICT.2004.1435066
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-18
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Stress control Isolation technology MOSFETs Tensile stress Lattices Tensile strain System-on-a-chip Costs Ultra large scale integration Filling
Content Type	Text
Resource Type	Article

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Scaling of shallow trench isolation with stress control for 65nm node and beyond