NDLI: Evaluation of sSOI wafers for 22nm node and beyond

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2015 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

2014 SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

2013 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S)

2012 IEEE International SOI Conference (SOI)

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Introduction and history [1975-2011]

Presentation listing

Evolution and expansion of SOI in VLSI technologies: Planar to 3D

Simply fundamental innovation for complex technology challenges — Case of smarttools

ARM physical IP overview

Key enabling processes for more-than-moore technologies

28nm FDSOI offer for academia and industry

BSIM-IMG: A Turnkey compact model for fully depleted technologies

High mobility p-n junction-less InGaAs-OI tri-gate nMOSFETs with metal source/drain for ultra-low-power CMOS applications

First demonstration of threshold voltage control by sub-1V back-gate biasing for thin body and buried-oxide (TBB) Ge-on-insulator (GOI) MOSFETs for low-power operation

First demonstration of drain current enhancement in SOI tunnel FET with vertical-tunnel-multiplication

Simulation analysis of process-induced variability in nanoscale SOI and bulk FinFETs

20 nm FDSOI process and design platforms for high performance/ low power systems on chip

Comparison between <100> and <110> oriented channels in highly strained FDSOI pMOSFETs

Ground plane optimization for 20nm FDSOI transistors with thin Buried Oxide

Taking the next step on advanced HKMG SOI technologies — From 32nm PD SOI volume production to 28nm FD SOI and beyond

Statistical variability in scaled generations of n-channel UTB-FD-SOI MOSFETs under the influence of RDF, LER, OTF and MGG

Experimental study of tri-gate SOI-FinFET flash memory

A little known benefit of FinFET over Planar MOSFET in highperformance circuits at advanced technology nodes

Sensing magnetic fields in any direction using FinFETs and L-gate FinFETs

Effectiveness of strained-Si technology for thin-body MOSFETs

Quasi-double gate mode for sleep transistors in UTBB FD SOI low-power high-speed applications

Flexible V FinFETs with 9-nm-thick extremely-thin BOX

Radiation hardness aspects of advanced FinFET and UTBOX devices

Design improvement of L-shaped tunneling field-effect transistors

Total-ionizing-dose radiation response of 32 nm partially and 45 nm fully-depleted SOI devices

Biaxial + uniaxial stress effectiveness in tri-gate SOI nMOSFETs with variable fin dimensions

Cryogenic operation of double-gate FinFET and demonstration of analog circuit at 4.2K

Liquid helium temperature analog operation of asymmetric self-cascode FD SOI MOSFETs

Gate length impact on UTBOX FBRAM devices

Low-Frequency Noise of nMOS and pMOS short channel junctionless nanowire transistors

Combined effect of mechanical stressors and channel orientation on mobility in FDSOI n and p MOSFETs

Improvement of high-frequency FinFET performance by fin width engineering

Improving the accuracy of numerically controlled sacrificial plasma oxidation using array of electrodes to improve the thickness uniformity of SOI

Experimental analog performance of pTFETs as a function of temperature

The role of the incomplete ionization on the operation of Junctionless Nanowire Transistors

Optimized CMOS-SOI process for high performance RF switches

Innovative tunable antenna solution using CMOS SOI technology

X-band receiver module in fully depleted silicon on insulator technology

Impact of back-gate bias on DC and RF characteristics in SiGe:C HBTs fabricated on thin-film SOI

Monolithic 2.5kV RMS, 1.8V–3.3V dual-channel 640Mbps digital isolator in 0.5μm SOS

Performance analysis and optimization for silicon interposer with Through Silicon Via (TSV)

Innovative capacitorless SOI DRAMs

Experimental demonstration of A2RAM memory cell on SOI

6T SRAM design for wide voltage range in 28nm FDSOI

Origin of wide retention distribution in 1T Floating Body RAM

Physics and design of a SOI Field-Effect-Diode memory cell

SOI tri-gate nanowire MOSFETs for ultra-low power LSI

Evaluation of sSOI wafers for 22nm node and beyond

GaN HEMTs on silicon for power devices

Mode engineering for hybrid SOI/III-V optical devices

Resonant Body Transistors in IBM's 32nm SOI CMOS technology

Design and materials selection for low power laterally actuating nanoelectromechanical relays

SOI for MEMS and advanced packaging

High voltage SOI MESFETs at the 45nm technology node

RF SOI CMOS technology on commercial trap-rich high resistivity SOI wafer

IEEE 2011 International SOI Conference

2010 IEEE International SOI Conference (SOI)

2009 IEEE International SOI Conference

2008 IEEE International SOI Conference

2007 IEEE International SOI Conference

2006 IEEE international SOI Conferencee Proceedings

2005 IEEE International SOI Conference Proceedings

2004 IEEE International SOI Conference (IEEE Cat. No.04CH37573)

2003 IEEE International Conference on SOI

2002 IEEE International SOI Conference

2001 IEEE International SOI Conference. Proceedings (Cat. No.01CH37207)

2000 IEEE International SOI Conference. Proceedings (Cat. No.00CH37125)

1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345)

1998 IEEE International SOI Conference Proceedings (Cat No.98CH36199)

1997 IEEE International SOI Conference Proceedings

1996 IEEE International SOI Conference Proceedings

1995 IEEE International SOI Conference Proceedings

Proceedings. IEEE International SOI Conference

Proceedings of 1993 IEEE International SOI Conference

1992 IEEE International SOI Conference

1991 IEEE International SOI Conference Proceedings

Evaluation of sSOI wafers for 22nm node and beyond

Content Provider	IEEE Xplore Digital Library
Author	Allibert, F. Cheng, K. Vinet, M. Schwarzenbach, W. Khakifirooz, A. Ecarnot, L. Nguyen, B.Y. Doris, B.
Copyright Year	2012
Description	Author affiliation: IBM Research at Albany Nanotech (Cheng, K.; Khakifirooz, A.; Doris, B.) \|\| CEA-Léti, 257 Fuller Rd, 12203 Albany, USA (Vinet, M.) \|\| Soitec, Parc Technologique des Fontaines - Bernin, 38926 Crolles - France (Allibert, F.; Schwarzenbach, W.; Ecarnot, L.; Nguyen, B.Y.)
Abstract	The transition to fully-depleted (FD) transistor technology is taking place today, either towards planar architectures on SOI wafers [1] or towards 3D-like architectures (FinFET or Trigate) [2]. The reason for this change is better electrostatic control, and reduction or even complete elimination of random dopant fluctuations, leading to much improved Vt variability.
Starting Page	1
Ending Page	2
File Size	746188
Page Count	2
File Format	PDF
ISBN	9781467326902
ISSN	1078621X
e-ISBN	9781467326919
e-ISBN	9781467326896
DOI	10.1109/SOI.2012.6404397
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Performance evaluation Strain Logic gates Electrostatics Silicon Voltage measurement
Content Type	Text
Resource Type	Article

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