NDLI: A little known benefit of FinFET over Planar MOSFET in highperformance circuits at advanced technology nodes

Content Provider	IEEE Xplore Digital Library
Author	Sachid, A.B. Chenming Hu
Copyright Year	2012
Description	Author affiliation: Electrical Engineering and Computer Sciences, University of California Berkeley (Sachid, A.B.; Chenming Hu)
Abstract	Power dissipation and power density are limiting the maximum operating frequency of highperformance circuits. This has forced a change in the micro-architecture of processors. High frequency, complex single-core architectures are replaced by simpler multi-core architectures that operate at a lower frequency (Fig.1) [1–4]. At sub-22nm nodes, cooling even the multi-core processors using economical cooling options will be challenging due to increasing power density. Hence, there is an imminent need to identify sources with potential to address this issue at the device level so that the benefits can propagate to the circuit level. In this work, we discuss the difference in the difference in the nature of parasitic capacitance in FinFETs and Planar MOSFETs, and its significant impact on circuit performance. Ultra-Thin Body SOI (UTBSOI) MOSFETs [5] is used as an example for Planar MOSFETs.
Starting Page	1
Ending Page	2
File Size	786126
Page Count	2
File Format	PDF
ISBN	9781467326902
ISSN	1078621X
e-ISBN	9781467326919
e-ISBN	9781467326896
DOI	10.1109/SOI.2012.6404367
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FinFETs Density measurement Power system measurements Logic gates Inverters Parasitic capacitance
Content Type	Text
Resource Type	Article

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