NDLI: Key enabling processes for more-than-moore technologies

Content Provider	IEEE Xplore Digital Library
Author	Lindner, P. Glinsner, T. Uhrmann, T. Dragoi, V. Plach, T. Matthias, T. Pabo, E. Wimplinger, M.
Copyright Year	2012
Description	Author affiliation: EV Group, DI Erich Thallner Str. 1, 4782 St. Florian am Inn, Austria (Lindner, P.; Glinsner, T.; Uhrmann, T.; Dragoi, V.; Plach, T.; Matthias, T.; Pabo, E.; Wimplinger, M.)
Abstract	The continuation of Moore's law by conventional complementary metal oxide semiconductor (CMOS) scaling is becoming more and more challenging, requiring huge capital investments. 3D-IC with through-silicon via (TSV) interconnects provides another path towards “More Than Moore” with relatively smaller capital investment. Recent announcements from leading image sensor and memory manufacturers show that 3D-ICs are finally moving into highvolume manufacturing (HVM) putting “More Than Moore” in reality. Wafer bonding is the enabling process technology to make this happen. Two of the key wafer bonding techniques — low temperature fusion bonding as well as temporary bonding and de-bonding are the major subject of this contribution, introducing basic process flows and working principles for their CMOS integration.
Starting Page	1
Ending Page	2
File Size	728340
Page Count	2
File Format	PDF
ISBN	9781467326902
ISSN	1078621X
e-ISBN	9781467326919
e-ISBN	9781467326896
DOI	10.1109/SOI.2012.6404360
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Plasma temperature Bonding Wafer bonding Surface treatment Annealing fusion bonding More-than-Moore temporary bonding debonding low-temperature direct bonding
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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