NDLI: Simulation analysis of process-induced variability in nanoscale SOI and bulk FinFETs

Content Provider	IEEE Xplore Digital Library
Author	Brown, A.R. Daval, N. Bourdelle, K.K. Nguyen, B. Asenov, A.
Copyright Year	2012
Description	Author affiliation: Gold Standard Simulation Ltd., Rankine Building, Glasgow G12 8LT, UK (Brown, A.R.; Asenov, A.) \|\| Soitec, Parc Technologique des Fontaines - Bernin, 38926 Crolles - France (Daval, N.; Bourdelle, K.K.; Nguyen, B.)
Abstract	Variability has become a major concern, forcing the industry to consider new transistor architectures for the 22nm technology generation and below [1]. Fully depleted thin-body transistors with improved electrostatic integrity tolerate an undoped channel promising significant reduction of the random-dopant component of the statistical variability. The implementation of such transistors in future CMOS technology generations will further push the scaling limits by enabling Vdd reduction and shorter gate lengths, provided that the overall variability of these devices is effectively improved. In fully depleted architectures the electrostatic integrity and electrical characteristics are controlled by the thickness of the channel and, in the 3D case, its height and shape. The process control of these dimensions will play a critical role in the variability of the new technologies.
Starting Page	1
Ending Page	2
File Size	1053560
Page Count	2
File Format	PDF
ISBN	9781467326902
ISSN	1078621X
e-ISBN	9781467326919
e-ISBN	9781467326896
DOI	10.1109/SOI.2012.6404356
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-10-01
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	FinFETs Logic gates Electrostatics Doping Semiconductor process modeling Analytical models
Content Type	Text
Resource Type	Article

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