NDLI: Simulation of correlated line-edge roughness in multi-gate devices

Content Provider	IEEE Xplore Digital Library
Author	Xiaobo Jiang Runsheng Wang Ru Huang Jiang Chen
Copyright Year	2013
Description	Author affiliation: Inst. of Microelectron., Peking Univ., Beijing, China (Xiaobo Jiang; Runsheng Wang; Ru Huang) \|\| Dept. of Electron., Peking Univ., Beijing, China (Jiang Chen)
Abstract	In this paper, the impacts of correlated line-edge roughness (LER) are investigated. Experimental statistics indicate that, the LER of the two edges in Si channel (Fin or nanowire) have strong cross-correlation, depending on the fabrication process. An improved simulation method based on Fourier synthesis is used to generate pairs of LER sequences with certain cross-correlation. The results show that, device Vth distribution is strongly dependent on the cross-correlation, and can exhibit non-Gaussian distribution. Dual-peak distribution appears and enlarges the variation of Vth significantly. In addition, a new method to extend 2D LER into 3D LER is proposed for future LER investigation.
Starting Page	123
Ending Page	126
File Size	1368578
Page Count	4
File Format	PDF
ISBN	9781467357333
ISSN	19461569
e-ISBN	9781467357364
DOI	10.1109/SISPAD.2013.6650590
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-09-03
Publisher Place	UK
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Correlation Silicon Nanoscale devices Three-dimensional displays Correlation coefficient FinFETs Nanowire Variability Line-edge Roughness (LER) Line-width Roughness (LWR) FinFET
Content Type	Text
Resource Type	Article

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