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Investigations on Line-Edge Roughness (LER) and Line-Width Roughness (LWR) in Nanoscale CMOS Technology: Part II–Experimental Results and Impacts on Device Variability
| Content Provider | Semantic Scholar |
|---|---|
| Author | Wang, Runsheng Jiang, Xiaobo Fan, Jiewen Chen, Jiang Pan, David Z. Huang, Ru |
| Copyright Year | 2013 |
| Abstract | In the part I of this paper, the correlation between line-edge roughness (LER) and line-width roughness (LWR) is investigated by theoretical modeling and simulation. In this paper, process-dependence of the correlation between LER and LWR is studied. The experimental results indicate that both Si Fin and nanowire have strongly correlated LER/LWR, and the cross-correlation of two edges depends on the fabrication process. Based on the improved simulation method proposed in the Part I of this paper, the impacts of correlated LER/LWR in the channel of double-gate devices are investigated. The results show that Vth distribution strongly relies on cross-correlation, and can exhibit non-Gaussian distribution and/or multipeak distribution, which enlarges the Vth variation. |
| Starting Page | 3676 |
| Ending Page | 3682 |
| Page Count | 7 |
| File Format | PDF HTM / HTML |
| DOI | 10.1109/TED.2013.2283517 |
| Volume Number | 60 |
| Alternate Webpage(s) | http://www.cerc.utexas.edu/utda/publications/J46.pdf |
| Alternate Webpage(s) | https://doi.org/10.1109/TED.2013.2283517 |
| Journal | IEEE Transactions on Electron Devices |
| Language | English |
| Access Restriction | Open |
| Content Type | Text |
| Resource Type | Article |
