NDLI: An approach of dynamic bottleneck machine dispatching for semiconductor wafer fab

Content Provider	IEEE Xplore Digital Library
Author	Zhang Huai Jiang Zhibin Lee Yen-Fei Ko Chen-Pin Choo Ooi Tuck, L. Lim Lee Phing
Copyright Year	2007
Description	Author affiliation: Shanghai Jiao Tong Univ., Shanghai (Zhang Huai; Jiang Zhibin)
Abstract	This paper proposed a dynamic bottleneck dispatching (DBD) policy to consider the dynamic bottlenecks for semiconductor wafer fabrication system. The DBD policy adopted the multi-class priority queuing model and developed a procedure to assign lots to different priority classes. Each queuing lot was assigned to a priority class by 3 decision parameters, which could be optimized by the response surface method and a desirability function approach. A case study based on a local fab was described to examine the performance impact of the DBD policy measured by CT, Var CT, WIP, and TP. The results of the simulation experiments and analysis showed that the DBD policy is superior to the use of the static dispatching rules. In future work, the DBD policy could be integrated with manufacturing execution system (MES) for scheduling wafer fab.
Starting Page	1
Ending Page	4
File Size	1115739
Page Count	4
File Format	PDF
ISBN	9781424411412
ISSN	1523553X
DOI	10.1109/ISSM.2007.4446814
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2007-10-15
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Dispatching Fabrication Semiconductor device modeling Optimization methods Response surface methodology Reactive power Analytical models Performance analysis Manufacturing Job shop scheduling
Content Type	Text
Resource Type	Article
Subject	Industrial and Manufacturing Engineering Electronic, Optical and Magnetic Materials Electrical and Electronic Engineering

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