NDLI: Meeting fab cycle time commitment during production ramp

Content Provider	IEEE Xplore Digital Library
Author	Subramaniam, M. Chan Chih Ming Mohan, M.
Copyright Year	2005
Description	Author affiliation: Chartered Semicond. Mfg. (Subramaniam, M.; Chan Chih Ming; Mohan, M.)
Abstract	Balancing cycle time and capacity during production ramp is always a challenge. One method that can be used to achieve balance between these two is to maximize throughput on certain tools and emphasize compliance on cycle time, CT, for the balance of the other tools. Litho equipments being the most expensive equipment in a fab is used to maximize throughput. Once lots are out of Litho, the other area tools is to follow strictly on the CT compliance rules. Cycle time compliance rules requires the most delayed lots on a particular equipment type is to be executed first. Rate of execution on Litho equipment and rate of compliance on other tools is measured on daily basis. Our experiment indicates if the rate of execution in the Litho is at 85% and above while the compliance of rules on other tools is above 80%, we can achieve cycle time commits and meet the fab capacity requirement at the same time
Sponsorship	IEEE Electron Devices Soc. IEEE Components Packaging and Manuf. Technol. Soc., Semicond. Equip. & Mater. Int. (SEMI) Soc. of Appl. Phys. of Japan
Starting Page	311
Ending Page	314
File Size	281412
Page Count	4
File Format	PDF
ISBN	0780391438
DOI	10.1109/ISSM.2005.1513365
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2005-09-13
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Production Throughput Delay effects Foundries Scattering Motion measurement
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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Two approaches to determine appropriated fab manufacturing production plan by cycle-time and WIP energy

Cycle time management during production ramp-up

Simultaneous cycle-time reduction and output enhancement in a fully loaded foundry wafer fab

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Self-Calibrate two-step digital setup/hold time measurement

Target motion analysis using time delays measured from a nonlinear array

Time-delay estimation performance in a scattering medium

Cycle time prediction and control based on production line status and manufacturing data mining

Factory automation migration experience for foundry fab from 200 mm to 300 mm

Meeting fab cycle time commitment during production ramp

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