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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Tsung-ta Ho Bangzhi Liu Eichfeld, S. Kok-Keong Lew Mohney, S. Redwing, J. Mayer, T. |
| Copyright Year | 2007 |
| Description | Author affiliation: Pennsylvania State Univ., University Park (Tsung-ta Ho; Bangzhi Liu) |
| Abstract | This paper discusses the oxidation of p- and n-type silicon nanowires (SiNWs) grown by the vapor-liquid-solid (VLS) method and their integration into top-gated FETs. The oxidization of the as-grown SiNWs was carried out at 900degC in dry oxygen following standard cleaning process (SCI & SC2). The resulting $Si/SiO_{2}$ core-shell NWs were integrated into top-gated FETs where the $SiO_{2}$ shell served as the gate dielectric, and their subthreshold properties were measured to investigate the electrical properties of the $Si/SiO_{2}$ interface. Plan-view and cross-sectional transmission electron microscopy (TEM) analysis was used to study the oxide shell thickness of SiNWs. |
| Starting Page | 1 |
| Ending Page | 2 |
| File Size | 394912 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781424418916 |
| DOI | 10.1109/ISDRS.2007.4422515 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-12-12 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | FETs Silicon Nanowires Solids Hysteresis Interface states Oxidation Educational institutions Circuits Substrates |
| Content Type | Text |
| Resource Type | Article |
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