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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hoong-Shing Wong Kah-Wee Ang Lap Chan Keat-Mun Hoe Chih-Hang Tung Balasubramaniam, N. Weeks, D. Landin, T. Spear, J. Thomas, S.G. Samudra, G. Yee-Chia Yeo |
| Copyright Year | 2007 |
| Description | Author affiliation: Nat. Univ. of Singapore, Singapore (Hoong-Shing Wong; Kah-Wee Ang; Lap Chan) |
| Abstract | We report a new source/drain-extension-last (SDE-last) process flow to incorporate in situ doped and lattice-mismatched source/drain (S/D) stressors extremely close to the channel edge for increased strain and reduced series resistance. This process enables the introduction of S/D stressors with much larger than reported lattice-mismatch at the end of the front-end process, thereby minimizing the thermal budget experienced by highly strained heterostructures which could possibly relax strain. For the first demonstration of this concept, an in situ phosphorus- doped silicon-carbon (SiCP) SDE was employed and integrated in a SOI N-FET. A record-high substitutional carbon concentration of 2.1% was used to realize very significant strain effects. |
| Starting Page | 1 |
| Ending Page | 2 |
| File Size | 342064 |
| Page Count | 2 |
| File Format | |
| ISBN | 9781424418916 |
| DOI | 10.1109/ISDRS.2007.4422419 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-12-12 |
| Publisher Place | USA |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Capacitive sensors Thermal stresses Educational institutions Microelectronics Etching Manufacturing Silicon carbide Transconductance Silicon alloys Backscatter |
| Content Type | Text |
| Resource Type | Article |
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