NDLI: Noble Failure Analysis procedure for trench MOSFET technology devices through detail electrical parameter characterization and unique Fault Isolation technique

Content Provider	IEEE Xplore Digital Library
Author	Yahya, A.K. Yusof, N.T. Yusof, Y.M.
Copyright Year	2012
Description	Author affiliation: ON Semiconductor Sdn Bhd., Failure Analysis Laboratory, Lot 122, Senawang Industrial Estate, 70450 Seremban, Negeri Sembilan, W. Malaysia (Yahya, A.K.; Yusof, N.T.; Yusof, Y.M.)
Abstract	The demand for exponential improvement in MOSFET performance versus cost has driven the Industry to miniaturize the die size thus maximizing the die density per square inch of wafer, and exploring breakthroughs in the device design and the wafer fabrication processes. The conventional planar Gate structure on top of the silicon surface is now being replaced by vertical gate micro structure inside hundreds of trenches in the silicon itself. The smaller pitch between the Gates, the deeper Polysilicon Gate and the thinner Gate Oxide in the trenches demand new and improved procedure for Failure Analysis technique of such devices. The paper describes the detail of the electrical parameter characterization to determine the location of the defect in the structure, the unique Fault Isolation technique to identify the exact defect location, and the noble failure analysis technique to uncover the defect and the failure mechanism causing the specific electrical failure mode of the device. Electrical parameter characterization of the Leakage and the VTH parameters, Fault isolation technique using Backside and Topside PEM/OBIRCH, FIB circuit stitching procedure, and the progressive FIB/TEM technique are discussed.
Starting Page	1
Ending Page	6
File Size	1313289
Page Count	6
File Format	PDF
ISBN	9781467309806
ISSN	19461550
e-ISBN	9781467309837
DOI	10.1109/IPFA.2012.6306269
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-07-02
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Logic gates MOSFET circuits Metals Failure analysis Circuit faults Silicon Semiconductor diodes
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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