NDLI: Low phase noise Ku-band PLL-IC with −104.5dBc/Hz at 10kHz offset using SiGe HBT ECL PFD

Content Provider	IEEE Xplore Digital Library
Author	Tsutsumi, K. Komaki, M. Shimozawa, M. Suematsu, N.
Copyright Year	2009
Description	Author affiliation: Mitsubishi Electric Corp., 5-1-1, Ofuna, Kamakura, Kanagawa, 247-8501, Japan (Tsutsumi, K.; Komaki, M.; Shimozawa, M.; Suematsu, N.)
Abstract	This paper describes one of the lowest phase noise Ku-band PLL-IC below 10kHz offset region using 0.18µm SiGe-BiCMOS process. Since the phase frequency detector (PFD) generates the major portion of phase noise of total PLL in low offset frequency region, SiGe HBT emitter coupled logic (ECL) circuit is employed to reduce 1/f noise of the PFD. The fabricated PLL-IC achieves in-band phase noise of −104.5dBc/Hz at 10 kHz offset in Ku-band. The calculated FOM (Figure of Merit) of $−227.7dBc/Hz^{2}$ is the lowest value among the reported PLL-ICs at 10 kHz offset.
Starting Page	373
Ending Page	376
File Size	625640
Page Count	4
File Format	PDF
ISBN	9781424428014
DOI	10.1109/APMC.2009.5384526
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-12-07
Publisher Place	Singapore
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Phase noise Silicon germanium Germanium silicon alloys Heterojunction bipolar transistors Phase frequency detector Phase locked loops Coupling circuits Logic circuits Noise reduction Circuit noise flicker noise Phase Locked Loop Phase Frequency Detector Emitter Coupled Logic 1/f noise
Content Type	Text
Resource Type	Article

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