NDLI: Impact of body bias on the high frequency performance of partially depleted SOI MOSFETs

Content Provider	IEEE Xplore Digital Library
Author	Guo-Wei Huang Kun-Ming Chen Han-Yu Chen Chi-Huan Huang Chun-Yen Chang
Copyright Year	2008
Description	Author affiliation: Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu (Han-Yu Chen; Chi-Huan Huang; Chun-Yen Chang) \|\| Nat. Nano Device Labs., Hsinchu (Guo-Wei Huang; Kun-Ming Chen)
Abstract	SOI MOS technology has been slated as the future ULSI technology because of its advantages in terms of speed, isolation, density, yield and performance. The superior speed advantage of the SOI devices has attracted much attention in both digital and radio frequency applications. In recent years, a number of direct current analysis based on the body-tied configurations of SOI devices have been reported. It has been confirmed that the body-tied configuration is one of the most effective and practical methods of suppressing the floating body effect and realizing the stable operation in SOI circuits, because the body potential of an SOI MOSFET's is fixed. Body-tied configuration SOI MOSFET has therefore been employed for some crucial parts in circuits that require high stability such as dynamic circuits. However, to this date, high frequency performance of body-tied configuration SOI devices is mainly focused on the dynamic-threshold MOSFET in which the body of the device is tied to the gate. This particular device configuration makes the analysis of small-signal model complicated and does not reveal much insight into the body bias effect on the device high frequency performance. In this study, we investigated the impacts of body bias on the high frequency performance of PD SOI MOSFET and showed, for that both $f_{T}$ and $f_{max}$ are dependent on the body bias.
Starting Page	1
Ending Page	5
File Size	93171
Page Count	5
File Format	PDF
ISBN	9781424426416
DOI	10.1109/APMC.2008.4958640
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-16
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency MOSFETs Degradation Voltage Capacitance Impedance Circuits Silicon Scattering parameters Isolation technology
Content Type	Text
Resource Type	Article

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Comparison between Short Channel Bulk (Silicon) and Body-Tied Partially Depleted SOI nMOS for High Frequency Low Voltage Analog Circuit Design

Off-state leakage current modeling in low-power/high-performance partially-depleted (PD) floating-body (FB) SOI MOSFETs

The role of externally applied body-bias on the hot-carrier degradation of partially depleted SOI N-MOSFETs

The impact of an external body-bias on the hot-carrier degradation of Partially Depleted SOI N-MOSFETs at cryogenic temperatures

The impact of an external body-bias on the hot-carrier degradation of partially depleted SOI N-MOSFETs at cryogenic temperatures

High Temperature DC and RF Behavior of Partially Depleted SOI versus Deep n-Well Protected Bulk MOSFETs

Monte Carlo characterization of fabricated partially-depleted SOI MOSFETs: high-frequency performance

High performance partially depleted SOI using spike RTA

Effects of SOI film thickness on high-performance microprocessor by 0.13 /spl mu/m Partially-Depleted SOI CMOS technology

Impact of body bias on the high frequency performance of partially depleted SOI MOSFETs

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The role of externally applied body-bias on the hot-carrier degradation of partially depleted SOI N-MOSFETs

The impact of an external body-bias on the hot-carrier degradation of Partially Depleted SOI N-MOSFETs at cryogenic temperatures

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