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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Malik, P. Kumar, S.P. Chaujar, R. Gupta, M. Gupta, R.S. |
| Copyright Year | 2008 |
| Description | Author affiliation: Dept. of Electron. Sci., Univ. of Delhi, Delhi (Malik, P.; Kumar, S.P.; Chaujar, R.; Gupta, M.; Gupta, R.S.) |
| Abstract | In this work, the proposed GME-TRC MOSFET structure has been investigated for different negative junction depths (NJD) and different gate metal workfunction difference and its performance improvement over the TRC MOSFET is studied using ATLAS-3D and DEVEDIT-3D. The result clearly depicts that GME-TRC MOSFET exhibits superior performance as compared to TRC MOSFET in terms of threshold voltage roll-off, reduced punchthrough and DIBL; and improved switching speed of the device and current driving capabilities. Thus, the investigated device structure, in addition to providing SCEs suppression and hot carrier effect immunity, enhances the device reliability and performance in terms of the factors discussed earlier. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 91177 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424426416 |
| DOI | 10.1109/APMC.2008.4958124 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2008-12-16 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Ultra large scale integration MOSFET circuits Threshold voltage Degradation Hot carrier effects Transconductance Electronic mail Semiconductor materials Semiconductor devices Laboratories |
| Content Type | Text |
| Resource Type | Article |
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