NDLI: Low power quadrature-input programmable frequency divider

Content Provider	IEEE Xplore Digital Library
Author	Ka Fai Chang Cheng, K.-K.M.
Copyright Year	2008
Description	Author affiliation: Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Hong Kong (Ka Fai Chang; Cheng, K.-K.M.)
Abstract	Quadrature-phase clock signals are essential for in-phase and quadrature-phase (IQ) mixing in direct-conversion wireless transceiver systems. One way to generate such signals is to use quadrature VCO (QVCO). Many techniques have been reported to improve the IQ phase mismatch of the QVCO. However, in practical application, the imbalance of the QVCO output loading, which is normally due to the input capacitance of the frequency divider, will seriously deteriorate the IQ phase matching. In most of the frequency divider architectures, only differential input signals are needed. In order to balance the QVCO output loading, a dummy divider is usually connected to the remaining pair of QVCO outputs. The dummy divider is also advised to be turned on so that it will provide identical loading condition as that of the main divider. In this way, the capacitive loading between the QVCO outputs can be properly balanced. Its major drawback is the increased chip area and power consumption due to the dummy divider. In this work, a new quadrature-input programmable frequency divider design is proposed and fabricated in a 0.35 mum standard CMOS process. The novel quadrature-input divide-by-8 injection-locked frequency divider (ILFD) offers several advantages, such as reduced power consumption, providing balance capacitive loading for QVCO, and generating unique 45deg- spaced phase sequence for subsequent phase-switching. Together with backward-phase- selection scheme, the glitch problem is solved without power-hungry synchronizing circuit.
Starting Page	1
Ending Page	4
File Size	183106
Page Count	4
File Format	PDF
ISBN	9781424426416
DOI	10.1109/APMC.2008.4957880
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-12-16
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Frequency conversion Energy consumption Clocks Transceivers Signal generators Voltage-controlled oscillators Capacitance CMOS process Power generation Frequency synchronization
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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