NDLI: A Space-Time Multiplex Architecture for 3D Stacked Embedded Vision Systems

Content Provider	IEEE Xplore Digital Library
Author	Schmidt, M. Loos, A. Fey, D.
Copyright Year	2006
Description	Author affiliation: Inst. of Comput. Sci., Friedrich-Schiller-Univ., Jena (Schmidt, M.; Loos, A.; Fey, D.)
Abstract	Due to the increasing needs of always faster automation technology in the field of industrial fabrication the common methods of machine vision meet their limits. The reasons are the widely used serial computation and transmission of data streams on the base of strict spatially separated data capturing by an image sensor and data processing, e.g. by a coupled DSP. To meet serious real time requirements many discrete high speed components are used which often causes high costs. In contrast we propose a 3D architecture based on stacked chip dies. In order to find a trade-off between speed and required chip area we present a space-time multiplex architecture, i.e. clusters of pixels are processed time-serially by one processor and several clusters are processed by a multi-core processor. Our architecture allows the successive computation of basic low-level image processing operations. We determined an optimal number of serially processed pixels between 16 and 32 in a cluster for a resolution of 256times256 pixels. Furthermore we found out that the most efficient way is to process a line based cluster
Sponsorship	IEEE CSP
Starting Page	374
Ending Page	379
File Size	323353
Page Count	6
File Format	PDF
ISBN	0769525547
DOI	10.1109/PARELEC.2006.10
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-13
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Machine vision Computer architecture Automation Space technology Textile industry Fabrication Streaming media Image sensors Data processing Couplings
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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