NDLI: Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels

Content Provider	IEEE Xplore Digital Library
Author	Siegel, S. Schaffer, R. Merker, R.
Copyright Year	2006
Description	Author affiliation: Inst. of Circuits & Syst., Dresden Univ. of Technol. (Siegel, S.; Schaffer, R.; Merker, R.)
Abstract	In this paper we derive an efficient realization of the edge detection algorithm on a target architecture with parallelism on two levels. Our target architecture is a processor array where parallelism is achieved 1) within the processing elements by sub-word parallelism (SWP) and 2) within the processor array by an arrangement of several processing elements. We exploit the parallelism on both levels of our processor array by a parameterized two-level partitioning of the algorithm. To obtain a significant speed-up such partitioning parameters are selected which match the target architecture and require a minimum number of additional instructions for SWP. Through this partitioning communication within the processor array appears to be necessary on a large scale. By a detailed examination, which is automatically performed by integer linear programming, we extract and eliminate redundant communication. Hence, our realization of the edge detection algorithm is efficient in terms of energy consumption caused by communication within the processor array. And we obtain a significant speed-up by exploiting both levels of parallelism
Sponsorship	IEEE CSP
Starting Page	173
Ending Page	180
File Size	286170
Page Count	8
File Format	PDF
ISBN	0769525547
DOI	10.1109/PARELEC.2006.33
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-13
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Image edge detection Parallel processing Partitioning algorithms Energy consumption Computer architecture Electronic design automation and methodology Circuits and systems Large-scale systems Integer linear programming Signal processing
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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