NDLI: Hierarchical Parallelization of an H.264/AVC Video Encoder

Content Provider	IEEE Xplore Digital Library
Author	Rodriguez, A. Gonzalez, A. Malumbres, M.P.
Copyright Year	2006
Description	Author affiliation: Dept. of Comput. Eng., Tech. Univ. of Valencia (Rodriguez, A.; Gonzalez, A.)
Abstract	Last generation video encoding standards increase computing demands in order to reach the limits on compression efficiency. This is particularly the case of H.264/AVC specification that is gaining interest in industry. We are interested in applying parallel processing to H.264 encoders in order to fulfill the computation requirements imposed by stressing applications like video on demand, videoconference, live broadcast, etc. Given a delivered video quality and bit rate, the main complexity parameters are image resolution, frame rate and latency. These parameters can still be pushed forward in such a way that special purpose hardware solutions are not available. Parallel processing based on off-the-shelf components is a more flexible general purpose alternative. In this work we propose a hierarchical parallelization of H.264 encoders very well suited to low cost clusters. Our proposal uses MPI message passing parallelization at two levels: GOP and frame. The GOP level encodes simultaneously several groups of consecutive frames and the frame level encodes in parallel several slices of one frame. In previous work we found that GOP parallelism alone gives good speed-up but imposes very high latency, on the other side frame parallelism gets less efficiency but low latency. Combining both approaches we obtain a compromise between speed-up and latency and then a broader spectrum of applications can be covered
Sponsorship	IEEE CSP
Starting Page	363
Ending Page	368
File Size	156897
Page Count	6
File Format	PDF
ISBN	0769525547
DOI	10.1109/PARELEC.2006.42
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2006-09-13
Publisher Place	Poland
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Automatic voltage control Parallel processing Delay Video compression Video on demand Encoding Concurrent computing Videoconference Multimedia communication Broadcasting
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Optimal Combination of H.264/AVC Coding Tools for Mobile Multimedia Broadcasting Application

Software parallel CAVLC encoder based on stream processing

Simplified NAL decoder for H.264/AVC baseline profile

Data partition for wavefront parallelization of H.264 video encoder

ILP platform optimization of a YAPI parallel H.264/AVC encoder

Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform

A Parallel and Pipelined Execution of H.264/AVC Intra Prediction

Data hiding for error concealment in H.264/AVC

Subjective performance evaluation of the SVC extension of H.264/AVC

Hierarchical Parallelization of an H.264/AVC Video Encoder

Similar Documents

Optimal Combination of H.264/AVC Coding Tools for Mobile Multimedia Broadcasting Application

Software parallel CAVLC encoder based on stream processing

Simplified NAL decoder for H.264/AVC baseline profile

Data partition for wavefront parallelization of H.264 video encoder

ILP platform optimization of a YAPI parallel H.264/AVC encoder

Mapping of H.264/AVC Encoder on a Hierarchical Chip Multicore DSP Platform

A Parallel and Pipelined Execution of H.264/AVC Intra Prediction

Data hiding for error concealment in H.264/AVC

Subjective performance evaluation of the SVC extension of H.264/AVC

Hierarchical Parallelization of an H.264/AVC Video Encoder