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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Hung-Ju Wei Chinchun Meng YuWen Chang Yi-Chen Lin Guo-Wei Huang |
| Copyright Year | 2007 |
| Description | Author affiliation: Dept. of Commun. Eng., Nat. Chiao Tung Univ., Hsinchu (Hung-Ju Wei; Chinchun Meng; YuWen Chang; Yi-Chen Lin; Guo-Wei Huang) |
| Abstract | This paper demonstrates the Divide-by-4/5 prescalers with merged AND gates in 2 mum GalnP/GaAs heterojunction bipolar transistor (HBT) and 0.35 mum SiGe HBT technologies. By biasing the HBT near the peak transit-time frequency (fr), the maximum operating frequency of a D-type flip-flop (D-FF) can be promoted. At the supply voltage of 5 V, the GalnP/GaAs prescaler operates from 30 MHz to 5.2 GHz, and the SiGe prescaler has the higher-speed performance of 1 GHz ~ 8 GHz at the cost of power consumption. |
| Starting Page | 1 |
| Ending Page | 4 |
| File Size | 2103508 |
| Page Count | 4 |
| File Format | |
| ISBN | 9781424407484 |
| DOI | 10.1109/APMC.2007.4554716 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2007-12-11 |
| Publisher Place | Thailand |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Heterojunction bipolar transistors Topology Gallium arsenide Silicon germanium Germanium silicon alloys Frequency Flip-flops Voltage Costs Energy consumption Emitter Couple Logic (ECL) GaInP/GaAs HBT SiGe HBT Dual-Modulus Divide-by-4/5 Prescaler |
| Content Type | Text |
| Resource Type | Article |
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