NDLI: The use of prediction for accelerating upgrade misses in cc-NUMA multiprocessors

Content Provider	IEEE Xplore Digital Library
Author	Acacio, M.E. Gonzalez, J. Garcia, J.M. Duato, J.
Copyright Year	2002
Description	Author affiliation: Univ. de Murcia, Spain (Acacio, M.E.; Gonzalez, J.; Garcia, J.M.; Duato, J.)
Abstract	This work is focused on accelerating upgrade misses in cc-NUMA multiprocessors. These misses are caused by store instructions for which a read-only copy of the line is found in the L2 cache. Upgrade misses require a message sent from the missing node to the directory, a directory lookup in order to find the set of sharers, invalidation messages being sent to the sharers and responses to the invalidations being sent back. Therefore, the penalty paid by these misses is not negligible, mainly if we consider that they account for a high percentage of the total miss rate. We propose the use of prediction as a means of providing cc-NUMA multiprocessors with a more efficient support for upgrade misses by directly invalidating sharers from the missing node. Our proposal comprises an effective prediction scheme achieving high hit rates as well as a coherence protocol extended to support the use of prediction. Our work is motivated by two key observations: first, upgrade misses present a repetitive behavior and, second, the total number of sharers being invalidated is small (one, in some cases). Using execution-driven simulations, we show that the use of prediction can significantly accelerate upgrade misses (latency reductions of more than 40% in some cases). These important improvements translate into speed-ups on application performance up to 14%. Finally, these results can be obtained including a predictor with a total size of less than 48 KB in every node.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Comput Archit. IEEE Comput. Soc. Tech. Committee on Parallel Process. ACM Special Interest Group on Comput. Architecture IFIP WG 10.3 IBM Microsoft Res. Univ. Virginia Dept. Comput. Sci
Starting Page	155
Ending Page	164
File Size	357588
Page Count	10
File Format	PDF
ISBN	0769516203
ISSN	1089795X
DOI	10.1109/PACT.2002.1106014
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-09-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Acceleration Delay Proposals Access protocols Predictive models Coherence Out of order Hardware
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Hardware and Architecture Software

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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