NDLI: Transparent threads: resource sharing in SMT processors for high single-thread performance

Content Provider	IEEE Xplore Digital Library
Author	Dorai, G.K. Yeung, D.
Copyright Year	2002
Description	Author affiliation: Electr. & Comput. Eng. Dept., Univ. of Maryland, College Park, MD, USA (Dorai, G.K.; Yeung, D.)
Abstract	To realize transparent threads, we propose three mechanisms for maintaining the transparency of background threads: slot prioritization, background thread instruction-window partitioning, and background thread flushing. In addition, we propose three mechanisms to boost background thread performance without sacrificing transparency: aggressive fetch partitioning, foreground thread instruction-window partitioning, and foreground thread flushing. We implement our mechanisms on a detailed simulator of an SMT processor and evaluate them using 8 benchmarks, including 7 from the SPEC CPU2000 suite. Our results show when cache and branch predictor interference are factored out, background threads introduce less than 1% performance degradation on the foreground thread Furthermore, maintaining the transparency of background threads reduces their throughput by only 23% relative to an equal priority scheme. To demonstrate the usefulness of transparent threads, we study transparent software prefetching (TSP), an implementation of software data prefetching using transparent threads. Due to its near-zero overhead, TSP enables prefetch instrumentation for all loads in a program, eliminating the need for profiling. TSP without any profile information, achieves a 9.52% gain across 6 SPEC benchmarks, whereas conventional software prefetching guided by cache-miss profiles increases performance by only 2.47%.
Sponsorship	IEEE Comput. Soc. Tech. Committee on Comput Archit. IEEE Comput. Soc. Tech. Committee on Parallel Process. ACM Special Interest Group on Comput. Architecture IFIP WG 10.3 IBM Microsoft Res. Univ. Virginia Dept. Comput. Sci
Starting Page	30
Ending Page	41
File Size	374978
Page Count	12
File Format	PDF
ISBN	0769516203
ISSN	1089795X
DOI	10.1109/PACT.2002.1105971
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2002-09-25
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Yarn Resource management Surface-mount technology Prefetching Interference Degradation Throughput Instruments Performance gain Software performance
Content Type	Text
Resource Type	Article
Subject	Theoretical Computer Science Hardware and Architecture Software

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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