NDLI: Development of ASICs for CdTe pixel and line sensors

Content Provider	IEEE Xplore Digital Library
Author	Tamura, K. Hiruta, T. Inoue, H. Kobayashi, Y. Takahashi, T. Ikeda, H. Kiyuna, T. Nakazawa, K. Takashima, T.
Copyright Year	2004
Description	Author affiliation: Inst. of Space & Astronaut. Sci., Sagamihara, Japan (Tamura, K.; Hiruta, T.; Inoue, H.; Kobayashi, Y.; Takahashi, T.)
Abstract	We are developing analog ASICs for Cadmium Telluride (CdTe) pixel and line sensors for high energy astrophysics and other applications. In the ASIC development, we are cooperating with other application users to build up a library of "tried-and-true" circuit modules tuned for several processes ("Open IP project"). As an initial trial, a 2-dimensional ASIC with a pixel size of 260 /spl mu/m /spl times/ 260 /spl mu/m and a 1-dimensional ASIC with an improved analog circuit, both based on 0.35-/spl mu/m CMOS technology, were developed and investigated. The readout system of the pixel ASIC worked properly, but the electric/electronic noise was too large compared with our final goals of 1keV (FWHM). With the latter ASIC, we have preliminarily obtained an energy resolution of 4.9 keV (FWHM) for 59.5 keV gamma-rays combined with a Schottky CdTe diode detector.
Starting Page	4528
Ending Page	4531
File Size	1348478
Page Count	4
File Format	PDF
ISBN	0780387007
ISSN	10823654
e-ISBN	0780387015
DOI	10.1109/NSSMIC.2004.1466890
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2004-10-16
Publisher Place	Italy
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Application specific integrated circuits CMOS technology Cadmium compounds Astrophysics Libraries Tuned circuits Analog circuits CMOS analog integrated circuits Circuit noise Energy resolution
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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