NDLI: Synergistic circuit and system design for energy-efficient and robust domain wall caches

Content Provider	IEEE Xplore Digital Library
Author	Motaman, S. Iyengar, A. Ghosh, S.
Copyright Year	2014
Description	Author affiliation: Comput. Sci. & Eng., Univ. of South Florida, Tampa, FL, USA (Motaman, S.; Iyengar, A.; Ghosh, S.)
Abstract	Non-volatile memories are gaining significant attention for embedded cache application due to their low standby power and excellent retention. Domain wall memory (DWM) is one possible candidate due to its ability to store multiple bits per cell in order to break the density barrier. Additionally, it provides low standby power, fast access time, good endurance and retention. However, it suffers from poor write latency, shift latency, shift power and write power. DWM is sequential in nature and latency of read/write operations depends on the offset of the bit from the read/write head. This paper investigates the circuit design challenges such as bitcell layout, head positioning, utilization factor of the nanowire, shift power, shift latency and provides solutions to deal with these issues. A synergistic system is proposed by combining circuit techniques such as merged read/write heads (for compact layout), flipped-bitcell and shift gating (for shift power optimization), wordline (WL) strapping (for access latency), shift circuit design with micro-architectural techniques such as segmented cache to realize energy-efficient and robust DWM cache. Simulations show 3-33% better performance and 1.25X-14.4X better power over a wide range of PARSEC benchmarks.
Starting Page	195
Ending Page	200
File Size	1050008
Page Count	6
File Format	PDF
DOI	10.1145/2627369.2627643
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-08-11
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Association for Computing Machinery, Inc. (ACM)
Subject Keyword	Metals Transistors Layout Decoding Magnetic heads Random access memory Routing synergistic systems Design Domain wall memory shift power cache segregation
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

Synergistic circuit and system design for energy-efficient and robust domain wall caches

Exploit common source-line to construct energy efficient domain wall memory based caches

DWM-TAPESTRI - An energy efficient all-spin cache using domain wall shift based writes

Design exploration of racetrack lower-level caches

Domain-wall memory buffer for low-energy NoCs

Design methodologies for high density domain wall memory

Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design

Perspectives of racetrack memory based on current-induced domain wall motion: From device to system

Adaptive Write and Shift Current Modulation for Process Variation Tolerance in Domain Wall Caches

Synergistic circuit and system design for energy-efficient and robust domain wall caches

Similar Documents

Synergistic circuit and system design for energy-efficient and robust domain wall caches

Exploit common source-line to construct energy efficient domain wall memory based caches

DWM-TAPESTRI - An energy efficient all-spin cache using domain wall shift based writes

Design exploration of racetrack lower-level caches

Domain-wall memory buffer for low-energy NoCs

Design methodologies for high density domain wall memory

Exploiting Serial Access and Asymmetric Read/Write of Domain Wall Memory for Area and Energy-Efficient Digital Signal Processor Design

Perspectives of racetrack memory based on current-induced domain wall motion: From device to system

Adaptive Write and Shift Current Modulation for Process Variation Tolerance in Domain Wall Caches

Synergistic circuit and system design for energy-efficient and robust domain wall caches