NDLI: Exploit common source-line to construct energy efficient domain wall memory based caches

Content Provider	IEEE Xplore Digital Library
Author	Xianwei Zhang Lei Zhao Youtao Zhang Jun Yang
Copyright Year	2015
Description	Author affiliation: Electr. & Comput. Eng. Dept., Univ. of Pittsburgh, Pittsburgh, PA, USA (Jun Yang) \|\| Comput. Sci. Dept., Univ. of Pittsburgh, Pittsburgh, PA, USA (Xianwei Zhang; Lei Zhao; Youtao Zhang)
Abstract	Domain wall memory (DWM) is an emerging memory technology that utilizes magnetic domains along a nanowire to achieve high density, short latency and low power. Recent studies showed that it is promising to replace SRAM and STT-MRAM to construct DWM based on-chip caches. However, accessing DWM requires frequent shift operations, which leads to large energy consumption for DWM caches. In this paper, we propose DWM-SSL, an architectural innovation to achieve energy efficiency for multiple-head based DWM caches. DWM-SSL adopts common source line design to re-organize DWM cell arrays such that accessing an N-bit cache line from M-head DWM based cache activates N/M tracks instead of N tracks in the baseline. Our experimental results show that, on average, DWM-SSL reduces around 5.1x track shifts and up to 63% cache energy consumption for a 4-head DWM cache design.
Sponsorship	IEEE
Starting Page	157
Ending Page	163
File Size	6393280
Page Count	7
File Format	PDF
e-ISBN	9781467371667
DOI	10.1109/ICCD.2015.7357097
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-10-18
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Magnetic heads Random access memory Energy consumption Magnetic domains Organizations Layout System-on-chip last level cache Domain wall memory
Content Type	Text
Resource Type	Article

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