NDLI: Analysis and implementation of low-cost FPGA-based digital pulse-width modulators

Content Provider	IEEE Xplore Digital Library
Author	de Leon, I. Sotta, G. Eirea, G. Acle, J.P.
Copyright Year	2014
Description	Author affiliation: Fac. de Ing., Univ. de la Republica, Montevideo, Uruguay (de Leon, I.; Sotta, G.; Eirea, G.; Acle, J.P.)
Abstract	This paper describes the architecture and operating principles of two digital pulse-width modulator (DPWM) implementations for low-cost field-programmable gate arrays (FPGAs). Both architectures are based on a counter-comparator block to process the most significant bits (MSB) portion of the reference input, enriched with additional elements to enhance duty-cycle resolution according to the less significant bits (LSB). The first architecture described has already been reported in the literature, it uses the on-chip PLL blocks to generate fixed delays and a selector to choose the one corresponding with the desired duty-cycle. Post-fitting adjustments of PLL delays are required to compensate delay differences between the diverse signal paths across the selector. In the second architecture described, a serializer-deserializer (SERDES) module is used to serialize a thermometer-coded representation of the LSB portion of the input. This serialization technique is commonly used for data transmission on high-speed serial I/O data transmission standards like LVDS and is extensively supported by FPGA providers. Experimental results are presented for both architectures synthesized on standard low-cost FPGA chips, showing very good linearity and resolutions up to 1ns. The first architecture provides a moderately better resolution. The second architecture, on the other hand, is a much more robust solution as it requires no post-fitting delay adjustments.
Starting Page	1523
Ending Page	1528
File Size	444232
Page Count	6
File Format	PDF
ISBN	9781467363860
DOI	10.1109/I2MTC.2014.6861000
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-12
Publisher Place	Uruguay
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Phase locked loops Delays Calibration Modulation Linearity Routing LVDS DPWM FPGA serdes
Content Type	Text
Resource Type	Article

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