NDLI: Acceleration with FPGA for blocks and subblocks edge pattern classification in DCT domain images

Content Provider	IEEE Xplore Digital Library
Author	Vega-Pineda, J. Rivera-Mejia, J. Sandoval-Rodriguez, R. Trujillo-Schiaffino, G.
Copyright Year	2014
Description	Author affiliation: Div. de Estudios de Posgrado e Investig., Inst. Tecnol. de Chihuahua, Chihuahua, Mexico (Vega-Pineda, J.; Rivera-Mejia, J.; Sandoval-Rodriguez, R.; Trujillo-Schiaffino, G.)
Abstract	The discrete cosine transform (DCT) is widely used in many image applications and there are a high number of data bases with images stored in DCT-JPEG format. In this paper we present a hardware accelerator to perform a modified scheme to classify DCT blocks according to its edge orientation content but the classification performed in the compress domain. The efficient and simple solution consists of two combined steps. The first is a bidirectional conversion to different sizes of the DCT blocks, and the second is the edge classifier based on the subblocks DCT coefficients much like as would be performed at the spatial domain. The hardware accelerator explained in this article implements the before mentioned second step and its synthesis is based on Altera's FPGAs. The accelerator is capable of classify up to five different edge directions {0°, 45°, 90°, 135° and NB (Non Edge Block)} analyzing the DC coefficient of four 4×4 coefficients (pixels) subblocks which together form an 8x8 DCT block (JPEG Std.). The architecture of the small accelerator is presented together with the arithmetic, simulation and performance values resulting from its implementation. Images showing the block classification resulting from applying the scheme to them are also presented. The software version of the scheme is much simpler than other near similar content image classifiers, is because of this that a hardware implementation is intended. The scheme is oriented to applications where the feature extraction from compressed images is important.
Starting Page	707
Ending Page	712
File Size	1106958
Page Count	6
File Format	PDF
ISBN	9781467363860
DOI	10.1109/I2MTC.2014.6860834
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-05-12
Publisher Place	Uruguay
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Image edge detection Discrete cosine transforms Hardware Indexes Classification algorithms Niobium Field programmable gate arrays fpga performance Block edge compress domain processing discrete cosine transform (DCT) image feature extraction
Content Type	Text
Resource Type	Article

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