NDLI: VHDL modeling of FECG extraction from the composite abdominal ECG using Atificial Intelligence

Content Provider	IEEE Xplore Digital Library
Author	Hasan, M.A. Ibrahimy, M.I. Reaz, M. Uddin, M.J. Hussain, M.S.
Copyright Year	2009
Description	Author affiliation: Department of Electrical & Computer Engineering, International Islamic University Malaysia, 53100 Gombak, Malaysia (Hasan, M.A.; Ibrahimy, M.I.; Uddin, M.J.; Hussain, M.S.) \|\| Department of Electrical, Electronic & System Engineering, Universiti Kebangsaan Malaysia, 43600 UKM, Bangi, Malaysia (Reaz, M.)
Abstract	FECG (Fetal ECG) signal contains potentially precise information that could assist clinicians in making more appropriate and timely decisions during pregnancy and labour. The extraction and detection of the FECG signal from composite abdominal signals with powerful and advance methodologies is becoming a very important requirement in fetal monitoring. The purpose of this paper is to model the developed algorithms on FECG signal extraction using VHDL (Very High Speed Integrated Circuit Hardware Description Language) for FPGA (Field Programmable Gate Array) implementation from the abdominal ECG signal using Neural Network approach is to provide efficient and effective ways of separating FECG signal and its nature. The designed model has been synthesized and fitted into Altera's Stratix II EP2S15F484C3 using the Quartus II version 7.2 Web Edition. The method appears to be exceedingly robust, correctly isolate the FECG signal from abdominal ECG.
Starting Page	1
Ending Page	5
File Size	1504011
Page Count	5
File Format	PDF
ISBN	9781424435067
DOI	10.1109/ICIT.2009.4939637
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2009-02-10
Publisher Place	Australia
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Abdomen Electrocardiography Data mining Field programmable gate arrays Pregnancy Monitoring Integrated circuit modeling Very high speed integrated circuits Hardware design languages Neural networks
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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