NDLI: Pipelined Hardware Architecture for High-Speed Optical Flow Estimation Using FPGA

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2015 IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines

2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines

2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines

2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines

2011 IEEE 19th Annual International Symposium on Field-Programmable Custom Computing Machines

2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines

Table of Contents

Message from the General Chairs

Message from the Program Chairs

Steering Committee

Program Committee

Additional Reviewers

Fast and Efficient FPGA-Based Feature Detection Employing the SURF Algorithm

Accelerating Viola-Jones Face Detection to FPGA-Level Using GPUs

Accelerating the Nonuniform Fast Fourier Transform Using FPGAs

Increased Performace of FPGA-Based Color Classification System

Pipelined Hardware Architecture for High-Speed Optical Flow Estimation Using FPGA

Distributed Hardware-Based Microkernels: Making Heterogeneous OS Functionality a System Primitive

Improving the Robustness of a Softcore Processor against SEUs by Using TMR and Partial Reconfiguration

Energy-Aware Optimisation for Run-Time Reconfiguration

A Communication Aware Online Task Scheduling Algorithm for FPGA-Based Partially Reconfigurable Systems

Fine-Grained Partial Runtime Reconfiguration on Virtex-5 FPGAs

Combining Duplication, Partial Reconfiguration and Software for On-line Error Diagnosis and Recovery in SRAM-Based FPGAs

Hardware Acceleration of Approximate Tandem Repeat Detection

Rapid RNA Folding: Analysis and Acceleration of the Zuker Recurrence

Reaping the Processing Potential of FPGA on Double-Precision Floating-Point Operations: An Eigenvalue Solver Case Study

Performing Floating-Point Accumulation on a Modern FPGA in Single and Double Precision

Blocking LU Decomposition for FPGAs

Acceleration of a DWT-Based Algorithm for Short Exposure Stellar Images Processing on a HPRC Platform

A TDMA Ethernet Switch for Dynamic Real-Time Communication

Designing Modular Hardware Accelerators in C with ROCCC 2.0

SIRC: An Extensible Reconfigurable Computing Communication API

ShapeUp: A High-Level Design Approach to Simplify Module Interconnection on FPGAs

Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research

Automated Precision Analysis: A Polynomial Algebraic Approach

FPGA Circuit Synthesis of Accelerator Data-Parallel Programs

Impulse C vs. VHDL for Accelerating Tomographic Reconstruction

Integrating High-Level Synthesis into MPI

Interprocedural Placement-Aware Configuration Prefetching for FPGA-Based Systems

BURAQ: A Dynamically Reconfigurable System for Stateful Measurement of Network Traffic

A Memory-Efficient and Modular Approach for String Matching on FPGAs

A Large-Scale Architecture for Restricted Boltzmann Machines

A Heterogeneous FPGA Architecture for Support Vector Machine Training

A High-Speed and Memory Efficient Pipeline Architecture for Packet Classification

FARM: A Prototyping Environment for Tightly-Coupled, Heterogeneous Architectures

Highly Versatile DSP Blocks for Improved FPGA Arithmetic Performance

Using the Power Side Channel of FPGAs for Communication

Design of a Reconfigurable Hybrid Database System

A Comparative Study on the Architecture Templates for Dynamic Nested Loops

A Scripting Engine for Combining Design Transformations

A Design Methodology for Application Partitioning and Architecture Development of Reconfigurable Multiprocessor Systems-on-Chip

Enumeration of Bent Boolean Functions by Reconfigurable Computer

DPA Resistant AES on FPGA Using Partial DDL

Poster abstracts

Publisher's Information

2009 17th IEEE Symposium on Field Programmable Custom Computing Machines

2008 16th International Symposium on Field-Programmable Custom Computing Machines

15th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2007)

2006 14th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

13th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'05)

12th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003.

Proceedings. 10th Annual IEEE Symposium on Field-Programmable Custom Computing Machines

The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01)

Proceedings 2000 IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00871)

Seventh Annual IEEE Symposium on Field-Programmable Custom Computing Machines (Cat. No.PR00375)

Pipelined Hardware Architecture for High-Speed Optical Flow Estimation Using FPGA

Content Provider	IEEE Xplore Digital Library
Author	Seunghun Jin Dongkyun Kim Dung Duc Nguyen Jae Wook Jeon
Copyright Year	2010
Abstract	Optical flow is a motion field estimation method that has a wide range of applications. In this paper, we present a fully pipelined hardware architecture for high-speed optical flow estimation based on a full-search block matching algorithm. A census transform is applied to the corresponding pixels in the current and previous frame. The similarity between two census vectors within the search area is then computed by measuring the hamming distance. Macro blocks are generated based on the measured hamming distance values and the best match is determined by locating the block that has the smallest sum. The synthesis tool reported that the proposed system is capable of processing 400 standard VGA frames per second.
Starting Page	33
Ending Page	36
File Size	749143
Page Count	4
File Format	PDF
ISBN	9780769540566
e-ISBN	9781424471430
DOI	10.1109/FCCM.2010.14
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Hardware High speed optical techniques Image motion analysis Field programmable gate arrays Optical buffering Hamming distance Motion estimation Optical computing Computer architecture Buffer storage FPGA optical flow hardware architecture VHDL
Content Type	Text
Resource Type	Article

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