NDLI: Combining Duplication, Partial Reconfiguration and Software for On-line Error Diagnosis and Recovery in SRAM-Based FPGAs

Content Provider	IEEE Xplore Digital Library
Author	Ilias, A. Papadimitriou, K. Dollas, A.
Copyright Year	2010
Abstract	SRAM-based FPGAs are susceptible to Single-Event Upsets (SEUs) in radiation-exposed environments due to their configuration memory. We propose a new scheme for the diagnosis and recovery from upsets that combines i) duplication of the core to be protected, ii) partial reconfiguration to reconfigure the faulty part only, and iii) hardcore processor(s) for deciding when and which part will be reconfigured; executing the application in software instead of hardware during fault handling; and controlling the reconfiguration. A hardcore processor has smaller cross section and it is less susceptible than reconfigurable resources. Thus it can temporarily undertake the execution during upset conditions. Real experiments demonstrate that our approach is feasible and an area reduction of more than 40% over the dominant Triple Modular Redundancy (TMR) solution can be achieved at the cost of a reduction in the processing rate of the input.
Starting Page	73
Ending Page	76
File Size	221199
Page Count	4
File Format	PDF
ISBN	9780769540566
e-ISBN	9781424471430
DOI	10.1109/FCCM.2010.20
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2010-05-02
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Field programmable gate arrays Fault detection Fault diagnosis Hardware Application software Redundancy Costs Resource management Computer errors Single event transient Hardcore Processor Single-Event Upsets Duplication Partial reconfiguration
Content Type	Text
Resource Type	Article

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