NDLI: An Extensible I/O Subsystem

Content Provider	IEEE Xplore Digital Library
Author	Sukhwani, B. Forin, A. Pittman, R.N.
Copyright Year	2008
Description	Author affiliation: Microsoft Res., WA, USA (Forin, A.; Pittman, R.N.) \|\| Boston Univ., Boston, MA, USA (Sukhwani, B.)
Abstract	This paper provides an overview of the I/O subsystem of the eMIPS dynamically self-extensible processor. During execution, eMIPS can load additional logic blocks that perform a variety of functions, from adding new instructions to the base instruction set to controlling I/O pins. A dynamically loaded logic block that acts as an I/O peripheral to software is what we term an extensible I/O peripheral, and the resulting I/O subsystem an extensible I/O subsystem. Extensible I/O subsystems already exist for off-chip peripherals and busses. On eMIPS, this is now also realized to create loadable on-chip peripherals and bus interfaces. To realize the extensible I/O subsystem, we have made two changes to the existing design. First, we have added additional mechanisms for a newly loaded extensible on-chip peripheral to connect to the memory controller, to interact with system software in the discovery process, to obtain the I/O space and interrupt resources that it needs to operate correctly and finally to disconnect from it. Second, we have extended the security model to extensible on-chip peripherals and their software drivers. Privileged peripherals can request access to additional interface signals that are normally not available to non-privileged extensions. These signals allow access to physical memory, interrupt lines and I/O pins. Extensible on-chip peripherals can interact with system software via memory-mapped I/O and interrupts. Further, they can also add new I/O instructions to the processor's ISA.
Starting Page	269
Ending Page	270
File Size	107194
Page Count	2
File Format	PDF
ISBN	9780769533070
DOI	10.1109/FCCM.2008.34
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2008-04-14
Publisher Place	USA
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Fabrics Hardware Logic System-on-a-chip System software Instruction sets Pins Security Pipelines Control systems
Content Type	Text
Resource Type	Article

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1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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