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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Bechara, C. Berhault, A. Ventroux, N. Chevobbe, S. Lhuillier, Y. David, R. Etiemble, D. |
| Copyright Year | 2011 |
| Description | Author affiliation: Université Paris Sud, Laboratoire de Recherche en Informatique, Orsay, F-91405, France (Etiemble, D.) || CEA, LIST, Embedded Computing Laboratory, Gif-sur-Yvette, F-91191, France (Bechara, C.; Berhault, A.; Ventroux, N.; Chevobbe, S.; Lhuillier, Y.; David, R.) |
| Abstract | With the increase in the design complexity of MPSoC architectures and the need for more transistor/energy efficient processor architectures, designers are exploiting the parallelism at the thread level (TLP) through the implementation of embedded multithreaded processors. Moreover, future manycore architectures tend to use small footprint RISC cores. In this paper, we present a small footprint, scalar, in-order, 5-stage pipeline, interleaved multithreaded processor with 2 hardware thread contexts for embedded systems and SoC integration. Synthesis results in 40 nm TSMC shows that the multithreaded core area is only 19800 $μm^{2}$ and 13.97 kilogates, which is almost equal to a 4KB direct mapped cache memory according to CACTI 6.5 tool [1]. The IMT core has an augmentation of 73.2% in core area compared to the monothreaded core. The multithreaded core is validated by running a simple bubble-sort application and varying the L1 D$ memory. The average performance gain is 17% compared to the monothreaded core. |
| Starting Page | 685 |
| Ending Page | 690 |
| File Size | 940469 |
| Page Count | 6 |
| File Format | |
| ISBN | 9781457718458 |
| e-ISBN | 9781457718465 |
| e-ISBN | 9781457718441 |
| DOI | 10.1109/ICECS.2011.6122367 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-12-11 |
| Publisher Place | Lebanon |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Pipelines Instruction sets Context Multithreading Switches Registers Hardware RISC multithreaded processors interleaved multithreading System-on-Chip embedded systems |
| Content Type | Text |
| Resource Type | Article |
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