NDLI: Capacitance scaling aware power optimized register design and implementation on 28nm FPGA

Content Provider	IEEE Xplore Digital Library
Author	Banshal, S.K. Pandey, B. Brenda, S.J.
Copyright Year	2014
Description	Author affiliation: Dept. Of Comput. Sci., South Asian Univ., New Delhi, India (Banshal, S.K.; Pandey, B.; Brenda, S.J.)
Abstract	Power optimization is the main concern in designing. In this paper, capacitance scaling is implemented on register to optimize the power. Clock Power & Signal Power are independent of capacitance scaling. I/O Power & Leakage Power is varying with changing capacitance. There is 48.76% drop in I/O Power when we reduce capacitance from 512 pF to 256 pF. In case of reducing further to 128 pF there is 73.15% power reduction occurred. To go more further to reduce capacitance to 64 pF the reduction scale is going up to 85.34%. When we reduce the capacitance to 32 pF the reduction in power dissipation is 97.00%. This design is implemented on 28 nm Artix7 FPGA. The power consumption of this design is verified on XPower 14.6.
Starting Page	1
Ending Page	4
File Size	253352
Page Count	4
File Format	PDF
e-ISBN	9781479923526
DOI	10.1109/ICCCI.2014.6921838
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-01-03
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Capacitance Scaling Processor Register Energy Efficient Power demand Capacitance Registers Power dissipation Power Optimization Field programmable gate arrays Optimization Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
6	Contents and Copyright Issues	Queries related to content curation and copyright issues	content@ndl.gov.in
7	National Digital Library of India Club (NDLI Club)	Queries related to NDLI Club formation, support, user awareness program, seminar/symposium, collaboration, social media, promotion, and outreach	clubsupport@ndl.gov.in
8	Digital Preservation Centre (DPC)	Assistance with digitizing and archiving copyright-free printed books	dpc@ndl.gov.in
9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

I/O standard based power optimized processor register design on ultra scale FPGA

Capacitance and frequency scaling based energy efficient image inverter design on FPGA

Output load capacitance based low power implementation of UART on FPGA

IO standard based energy efficient ALU design and implementation on 28nm FPGA

FPGA low-power implementation of QRS detectors

Clock Gating Aware Low Power Global Reset ALU and Implementation on 28nm FPGA

Energy Efficient Counter Design Using Voltage Scaling on FPGA

Clock gating based energy efficient ALU design and implementation on FPGA

Energy efficient flip flop design using voltage scaling on FPGA

Capacitance scaling aware power optimized register design and implementation on 28nm FPGA

Similar Documents

I/O standard based power optimized processor register design on ultra scale FPGA

Capacitance and frequency scaling based energy efficient image inverter design on FPGA

Output load capacitance based low power implementation of UART on FPGA

IO standard based energy efficient ALU design and implementation on 28nm FPGA

FPGA low-power implementation of QRS detectors

Clock Gating Aware Low Power Global Reset ALU and Implementation on 28nm FPGA

Energy Efficient Counter Design Using Voltage Scaling on FPGA

Clock gating based energy efficient ALU design and implementation on FPGA

Energy efficient flip flop design using voltage scaling on FPGA

Capacitance scaling aware power optimized register design and implementation on 28nm FPGA