NDLI: I/O standard based power optimized processor register design on ultra scale FPGA

Content Provider	IEEE Xplore Digital Library
Author	Singh, P.R. Pandey, B. Kumar, T. Das, T.
Copyright Year	2014
Description	Author affiliation: Dept. of Comput. Sci., South Asian Univ., Delhi, India (Singh, P.R.; Pandey, B.; Kumar, T.; Das, T.)
Abstract	In design and implementation of energy efficient register, we are using different I/O standard in 28nm Artix-7 FPGA, Verilog, Xilinx ISE 14.6 as simulator and XPower 14.6 as energy estimator and analyzer tool. This register is a building block of energy efficient processor based on LVCMOS (Low Voltage Complementary Metal Oxide I/O, HSTL(High Speed Transistor Logic), HSUL standard in FPGA. This design is implemented on 28nm 7 Series Kintex-7 (7k70tfbg676-3) FPGA. When register operates in range of 1GHz-1THz, the reduction in I/O energy frittering of register for LVCMOS15 is 25.37%, 57.80%, 75.18% lesser of LVCMOS18, LVCMOS25 and LVCMOS33 respectively. When register operates at 1 GHz, the reduction in I/O energy dissipation of HSTL_II is 25.48%, 57.78%, 75.20% lesser of HSTL_I, HSTL_I_18 and HSTL_II_18 respectively. LVCMOS15 is the most energy efficient IO standard whereas LVCMOS33 is the worst energy fritter. HSTL_II is the least energy fritter I/O standards whereas HSTL_I_18 is the highest energy fritter among all available 4 different HSTL I/O standard.
Sponsorship	IEEE Delhi Sect.
Starting Page	172
Ending Page	177
File Size	14176922
Page Count	6
File Format	PDF
ISBN	9789380544106
e-ISBN	9789380544120
DOI	10.1109/IndiaCom.2014.6828123
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-03-05
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Bharati Vidyapeeth University
Subject Keyword	HSTL FPGA I/Os Energy Registers I/O standard Standards Equations Processor Register Ultra Power Design LVCMOS Energy efficiency Power dissipation Field programmable gate arrays Clocks
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
5	Website/Portal (Helpdesk)	Queries regarding NDLI and its services	support@ndl.gov.in
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9	IDR Setup or Support	Queries related to establishment and support of Institutional Digital Repository (IDR) and IDR workshops	idr@ndl.gov.in

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