NDLI: Energy efficient flip flop design using voltage scaling on FPGA

Content Provider	IEEE Xplore Digital Library
Author	Singh, S. Kaur, A. Pandey, B.
Copyright Year	2014
Description	Author affiliation: Sch. of Electron. Eng., Chitkara Univ., Rajpura, India (Kaur, A.; Pandey, B.) \|\| Sch. of Comput. Sci., Chitkara Univ., Rajpura, India (Singh, S.)
Abstract	In this work, we are using voltage scaling and frequency scaling. In voltage scaling, voltage is scaled from 3V to 1V, where intermediate values are 2.5V, 2V, 1.8V and 1.5V. In frequency scaling, frequency is scaled from 1 MHz to 1 THz, where intermediate values are 10 MHz, 100 MHz, 1 GHz, 10 GHz and 100 GHz. When we scale down device operating frequencies from 1THz to 1GHz, there is 72.9% reduction in power dissipation on Virtex-6 FPGA. When we scale down device operating frequencies from 1THz to 1GHz, there is 98.75% reduction in power dissipation on Virtex-4 FPGA. When we scale down device supply voltage from 3V to 2.5V, 2V, 1.8V and 1V, there is 82.23%, 96.83%, 98.45% and 99% reduction in power dissipation respectively on Virtex-6 FPGA on 10MHz device operating frequency. When we scale down device supply voltage from 3V to 2.5V, 2V, 1.8V and 1V, there is 74.42%, 92.67%, 94.71% and 97.66% reduction in power dissipation respectively on Virtex-6 FPGA on 1THz device operating frequency.
Starting Page	1
Ending Page	5
File Size	1079604
Page Count	5
File Format	PDF
ISBN	9781479960453
e-ISBN	9781479960460
DOI	10.1109/IICPE.2014.7115855
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2014-12-08
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy Efficient Design Device Operating Frequency VLSI FPGA Power dissipation Voltage Scaling Reliability Field programmable gate arrays Robots
Content Type	Text
Resource Type	Article

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