NDLI: Clock gating based energy efficient ALU design and implementation on FPGA

Content Provider	IEEE Xplore Digital Library
Author	Pandey, B. Yadav, J. Pattanaik, M. Rajoria, N.
Copyright Year	2013
Description	Author affiliation: Dept. of Comput. Sci., Indian Inst. of Technol., Hyderabad, Hyderabad, India (Rajoria, N.) \|\| Dept. of Inf. Technol., ABV-Indian Inst. of Inf. Technol. & Manage., Gwalior, India (Pandey, B.; Yadav, J.; Pattanaik, M.)
Abstract	In this paper, latch free clock gating techniques is applied in ALU to reduce clock power and dynamic power consumption of ALU. Clock power is 50%, 41.46%, 51.30%, 55.15% and 55.78% of total dynamic power when device operating frequency is 100MHz, 1GHz, 10GHz, 100GHz and 1 THz. After implementation of clock gating techniques in ALU, Clock power reduces to 17.85%, 23.39%, 26.49% and 27.19% of total dynamic power, when device operating frequency is 1GHz, 10GHz, 100GHz and 1 THz. On 1 THz operating frequency, when we use clock gating, there are 72.77% reduction in clock power, 38.88% reduction in IOs power and 44% reduction in dynamic power in compare to power consumption without using clock gating techniques. Target device is 90-nm Spartan-3. There is 14.57% reduction in junction temperature on 10GHz operating frequency in compare to temperature without using clock gating techniques. Clock gating saves power but increases over all area. There is 32.35%, 37.84%, 43.31% and 44% reduction in dynamic current when we use clock gate on 1GHz, 10GHz, 100GHz and 1THz operating frequency respectively.
Sponsorship	IEEE Madras Sect.
Starting Page	93
Ending Page	97
File Size	1000269
Page Count	5
File Format	PDF
ISBN	9781467361491
e-ISBN	9781467361507
DOI	10.1109/ICEETS.2013.6533362
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2013-04-10
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Energy Efficient Dynamic Current Power demand Conferences Registers Operating Frequency Low Power Logic gates Clock Gating Clock Power Junctions Field programmable gate arrays Clocks Dynamic Power
Content Type	Text
Resource Type	Article

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