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Content Provider | IEEE Xplore Digital Library |
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Author | Ji-zhe Yang Jian-de Lu |
Copyright Year | 2011 |
Description | Author affiliation: School of Computer Science and Technology, Soochow University, Suzhou, 215006, P.R China (Ji-zhe Yang; Jian-de Lu) |
Abstract | Traditional single-CPU based NIDS/NIPS are more and more difficult to deploy in the new generation network because of their less processing power. To meet the requirements of high-speed, high performance and high efficiency for NIDS/NIPS in the new generation network, the scheme of linked IPS based on Octeon multi-core processor is proposed, furthermore, the new intrusion characteristics occurring in IPv6 network are also considered. Matching rules in rule library for intrusion detection, and using the new protocol analysis and flow-based detection techniques, the multiple parallel executions including the executions on control plane and data plane are distributed on multiple cores of Octeon. Adopting the mechanism of named blocks to communicate between multiple cores, and by means of the feedbacks from the cores running data plane code to the control plane core, the system has realized the high-speed linking among the flow processing, protocol analysis and the control module. |
Starting Page | 1840 |
Ending Page | 1844 |
File Size | 331553 |
Page Count | 5 |
File Format | |
ISBN | 9781612847191 |
e-ISBN | 9781612847221 |
DOI | 10.1109/MEC.2011.6025842 |
Language | English |
Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Publisher Date | 2011-08-19 |
Publisher Place | China |
Access Restriction | Subscribed |
Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
Subject Keyword | Protocols Multicore processing IPv6 Process control Multi-core Libraries Software Octeon Joining processes IPS Linking Pipeline processing |
Content Type | Text |
Resource Type | Article |
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