NDLI: L2 Cache Performance Analysis and Optimizations for Processing HDF5 Data on Multi-core Nodes

Content Provider	IEEE Xplore Digital Library
Author	Bhowmik, R. Govindaraju, M.
Copyright Year	2012
Abstract	It is important to design and develop scientific middleware libraries to harness the opportunities presented by emerging multi-core processors that are available on grid and cloud environments. Scientific middleware libraries not adhering or adapting to this programming paradigm can suffer from severe performance limitations while executing on emerging multi-core processors. In this paper, we focus on the utilization of a critical shared resource on chip multiprocessors (CMPs), the L2 cache. The way in which an application schedules and assigns processing work to each thread determines the access pattern of the shared L2 cache, which may result in either enhancing or diminishing the effects of memory latency on a multi-core processor. Therefore, while processing scientific datasets such as HDF5, it is essential to conduct fine-grained analysis of cache utilization, to make informed processing and scheduling decisions in multi-threaded programming. In this paper, using the TAU toolkit for performance feedback from dual- and quad-core machines, we analyze and recommend methods for effective scheduling of threads on multi-core nodes to augment the performance of scientific applications processing HDF5 data. We discuss the benefits that can be achieved by using L2 Cache-Affinity and L2 Balanced-Set based scheduling algorithms for improving L2 cache performance and effectively the overall execution time.
Starting Page	142
Ending Page	149
File Size	350328
Page Count	8
File Format	PDF
ISBN	9781467316316
DOI	10.1109/ISPA.2012.27
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2012-07-10
Publisher Place	Spain
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	multi-core Multicore processing Processor scheduling Instruction sets L2 cache Hardware Libraries HDF5 Middleware Optimization
Content Type	Text
Resource Type	Article

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