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| Content Provider | IEEE Xplore Digital Library |
|---|---|
| Author | Chen Haifeng Du Huimin Guo Lixin |
| Copyright Year | 2011 |
| Description | Author affiliation: School of Electronic Engineering, Xi'an University of Posts and Telecommunications, Xi'an, China (Chen Haifeng; Du Huimin; Guo Lixin) |
| Abstract | The effect of substrate negative bias VB on the gate-induced drain leakage (GIDL) current is studied. It is found that the negative VB leads GIDL current curve shifts upwards. The shift of GIDL current ΔID/ID increases with increasing |VB|. The GIDL current at VG=−0.2V (in the low field region) increases with increasing |VB| more largely than that at VG=−1.2V (in the high field region). This is because that the negative VB results in the additional GIDL tunneling current in the lateral direction and it has the different effects on the low field region and high field region. It is also found that ΔID/ID at VD=0.8V is larger than that at VD=0.4V under VG=−1.2V and is smaller than that at VD=0.4V under VG=−0.2V. This ascribes the different roles of the GIDL vertical tunneling current and the GIDL lateral current induced by negative VB on the whole GIDL current. |
| Starting Page | 396 |
| Ending Page | 398 |
| File Size | 237870 |
| Page Count | 3 |
| File Format | |
| ISBN | 9781612847191 |
| e-ISBN | 9781612847221 |
| DOI | 10.1109/MEC.2011.6025484 |
| Language | English |
| Publisher | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Publisher Date | 2011-08-19 |
| Publisher Place | China |
| Access Restriction | Subscribed |
| Rights Holder | Institute of Electrical and Electronics Engineers, Inc. (IEEE) |
| Subject Keyword | Gate to drain Tunneling MOSFET circuits Logic gates Silicon CMOS integrated circuits GIDL Substrates Band to band |
| Content Type | Text |
| Resource Type | Article |
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