NDLI: Enhanced electromigration resistance through grain size modulation in copper interconnects

Content Provider	IEEE Xplore Digital Library
Author	Yang, C.-C. Li, B. Baumann, F.H. Huang, E. Edelstein, D. Rosenberg, R.
Copyright Year	2015
Description	Author affiliation: IBM Res., Albany, NY, USA (Yang, C.-C.; Li, B.; Baumann, F.H.; Huang, E.; Edelstein, D.; Rosenberg, R.)
Abstract	Grain size modulation in Cu interconnects was achieved at an elevated anneal temperature of 250 °C. As compared to the conventional annealing at 100 °C, the elevated process enabled further Cu grain growth, which then resulted in an increased grain size and improved electromigration resistance in the Cu interconnects. In order to prevent stress migration reliability degradation from the elevated annealing process, a TaN metal passivation layer was deposited on the Cu interconnect surface prior to the thermal annealing process, which suppressed void formation within the Cu features during the anneal process and reduced inelastic deformation within the interconnects after cooling down to room temperature.
Starting Page	1
Ending Page	5
File Size	1232341
Page Count	5
File Format	PDF
ISBN	9781479972418
ISSN	21582297
DOI	10.1109/CSTIC.2015.7153408
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-03-15
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Degradation Electromigration Grain size Annealing Planarization Cooling Simulated annealing Reliability Copper Stress Thermal degradation
Content Type	Text
Resource Type	Article

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4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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