NDLI: Investigation and solution of intermittent GOI failures at 40 nm CMOS devices

Content Provider	IEEE Xplore Digital Library
Author	Ming Zhou
Copyright Year	2015
Description	Author affiliation: Semicond. Manuf. Int. (Shanghai) Corp., Shanghai, China (Ming Zhou)
Abstract	Low k (dielectric constant) barrier (SiCN) is one of the most critical dielectric films used in Cu interconnects, and it has great impact on device reliability such as gate oxide integrity (GOI), plasma induced damage (PID), time-dependent dielectric breakdown (TDDB), electromigration (EM) and so on. This work was to investigate an intermittent GOI failure at 40nm CMOS devices, which was caused by low-k Cu barrier film deposition, and develop an improved process to resolve this issue. To understand the GOI failures, surface charge was collected at various process conditions. It was found, however, that the processes with the lowest surface charge and the best charge non-uniformity didn't improve GOI unexpectedly. The GOI issue was resolved instead by optimizing the RF ramp-up setting and inserting a novel enhanced nitride interface (ENI) layer (~30A). Further studies found that the GOI damage was primarily formed during the plasma ignition step and was related to instantaneous plasma non-uniformity. Well controlled plasma ignition and better Cu surface protection were the keys to achieve good GOI performance.
Starting Page	1
Ending Page	7
File Size	4014623
Page Count	7
File Format	PDF
ISBN	9781479972418
ISSN	21582297
DOI	10.1109/CSTIC.2015.7153406
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-03-15
Publisher Place	China
Access Restriction	Subscribed
Rights Holder	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Subject Keyword	Radio frequency Logic gates Silicon Manufacturing Transistors Antennas Substrates
Content Type	Text
Resource Type	Article

Sl.	Authority	Responsibilities	Communication Details
1	Ministry of Education (GoI), Department of Higher Education	Sanctioning Authority	https://www.education.gov.in/ict-initiatives
2	Indian Institute of Technology Kharagpur	Host Institute of the Project: The host institute of the project is responsible for providing infrastructure support and hosting the project	https://www.iitkgp.ac.in
3	National Digital Library of India Office, Indian Institute of Technology Kharagpur	The administrative and infrastructural headquarters of the project	Dr. B. Sutradhar bsutra@ndl.gov.in
4	Project PI / Joint PI	Principal Investigator and Joint Principal Investigators of the project	Dr. B. Sutradhar bsutra@ndl.gov.in Prof. Saswat Chakrabarti will be added soon
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