NDLI: Run time reconfigurable modified Vedic multiplier for high speed multimedia applications

Content Provider	IEEE Xplore Digital Library
Author	Sivanandam, K. Kumar, P.
Copyright Year	2015
Description	Author affiliation: Dept. of Electron. & Commun. Eng., K.S. Rangasamy Coll. of Technol., Namakkal, India (Sivanandam, K.; Kumar, P.)
Abstract	In this paper, a detector block is introduced to identify the unwanted portion of the input data to be processed in the data processing unit. Therefore data computation time is reduced in the detector based Vedic multiplier that supports full range and half range input data. The detector is developed based on Boolean function, to detect the valid ranges of two input operands during input data computation. The detector result is used to select the operand with half range input data for Vedic multiplication and it is disabled the surplus computation. So, it reduces the switching activities in the logic gates and proportionally reduces the power consumption. Including the detector unit, modified Vedic multiplier architecture is developed with less area overhead in case of both operands in full range computation. The Modified Vedic multiplier, which is used to compute 4 bit, 8 bit and 16 bit length input data are used to analysis the processing time and calculated number of active logic gates needed during multiplication. The proposed architecture reduces number of active logic gates from 43% to 76.25%. So, this proposed modified Vedic multiplier is placed in the mantissa part of the floating point number multiplication which is used to analysis real time application.
Starting Page	2109
Ending Page	2113
File Size	581972
Page Count	5
File Format	PDF
ISBN	9789380544151
e-ISBN	9789380544168
Language	English
Publisher	Institute of Electrical and Electronics Engineers, Inc. (IEEE)
Publisher Date	2015-03-11
Publisher Place	India
Access Restriction	Subscribed
Rights Holder	Bharati Vidyapeeth University, New Delhi
Subject Keyword	Power demand Truncated block multiplication Single precision Karatsuba multiplication Detector Double precision Signal processing algorithms Detectors Computer architecture Logic gates Floating point multiplier Real-time systems Modified Vedic multiplier Field programmable gate arrays
Content Type	Text
Resource Type	Article

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